low latency signal generation using timer and DMA

[con3]

Posted on April 30, 2018 at 21:20

Hey everyone,

I used a one pulse mode  master signal that triggers a slave timer. The slave timer then generates a one pulse waveform with repetition counter set to 5.

I want to generate the signal above, It receives a pulse called drdy and is fed by an external clock at a frequency of 24 MHz. After the DRDY pulse it should remain low for 16 rising edges of the external clock, then it should toggle a pin 12 times, each toggle after 8 clock pulses,after which it should stop till the next drdy pulse.

The latency on just using the timer to generate this is too long, I'd need the rise time and reaction of the signal to be sub 20 ns. Could I implement a DMA with the timer to generate this for very low latency?

Thanks in advance for any help!

#dma-normal #waveform-generator #aribtary-waveform #software-timer

[waclawek.jan]

Posted on April 30, 2018 at 23:27

I used a one pulse mode  master signal that triggers a slave timer. The slave timer then generates a one pulse waveform with repetition counter set to 5.

How is it relevant to the given problem?

The latency on just using the timer to generate this is too long

Latency between what and what, and in which timer of which STM32? Describe, how would you intend to implement it. Draw diagrams.

JW

[con3]

Posted on May 01, 2018 at 00:04

Hi

Waclawek.Jan

,

I used a one pulse mode master signal that triggers a slave timer. The slave timer then generates a one pulse waveform with repetition counter set to 5.

How is it relevant to the given problem?

This was what i used to generate the waveform above and sort of how I approached the problem.

When drdy went high It would trigger a timer which would remain low for 16 edges and then go high. Once it goes high it triggers a secondary timer in one pulse mode, It outputs a pulse with length 8 and period Which then repeats itself 6 times and the stops(using the repetition counter). The waveform came out correctly but was extremely low latency between periods where the counter would reach overflow and the transition of the gpio pin.

Here's a picture of the whole waveform(it repeats itself every time DRDY pulses):

How is it relevant to the given problem?

The latency on just using the timer to generate this is too long

Latency between what and what, and in which timer of which STM32? Describe, how would you intend to implement it. Draw diagrams.

JW

The latency is between the external clock that is going into ETR2 of Timer 8(which produces the 6 pulses) and 4(which triggers timer 8) on the stm32f722ze and its output when it reaches overflow. At merely 8 MHZ, it provides a latency of nearly half a clock cycle to transition.Shown below is a external clock frequency of 8MHz, at overflow it takes 44 nanoseconds to transition to a high state on timer8. This is with fast mode enabled and pins set to very high frequency

If I could at all generate a waveform that stays low for 16 rising edges of the external clock after the drdy pulse and then transitions on every 8 clock pulses of the external clock to generate 6 pulses with low latency between when overflow occurs and the pin is toggled I would be very happy.

Sorry if there is still any ambiguity, please let me know

[waclawek.jan]

Posted on May 01, 2018 at 00:47

So is the problem the delay at A, at B, at C, at all of them, or something else?

I suspect all of them, correct?

I am not very familiar with exact timing between ETR and the clock advancement; and between the compare event and output; and AFAIK this is not documented well if at all. There is certainly at least one synchronizer (i.e. delay between one to two timer clock, depending on the particular phase between external signal's edge and timer clock's edge) at the ETR input, and I suspect there may be at least one more between the compare unit and the output.  Start with a simple few-clock PWM driven from the external clock, and measure the latency, varying the timer clock (i.e. related APB clock, through the APB divider, or for that matter changing the system clock, whatever you find easier).

You may be better off deliberately delaying the whole pulse train by a whole external clock cycle, by setting a filter on ETR. That again is driven from the respective APB clock.

IMO DMA won't help you here: the input signal is again through timer i.e. at least the input portion of delay is still there; and the arbitration within the DMA and on the buses involves not only delay but also jitter (i.e. that delay is varying, depending on what does the rest of the system do).

JW