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regmaster2
regmaster2
Associate II
December 25, 2010
Question

Lib PLL configuration wrong for Connectivity Line

  • December 25, 2010
  • 2 replies
  • 650 views
Posted on December 25, 2010 at 12:18

Lib PLL configuration wrong for Connectivity Line

    This topic has been closed for replies.

    2 replies

    Tesla DeLorean
    Tesla DeLorean
    Guru
    May 17, 2011
    Posted on May 17, 2011 at 14:19

        /* PCLK1 = HCLK */

        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

    I think that should read PCLK1 = HCLK / 2

    Isn't the max clock for APB1 36 MHz, the timers taking an HCLK (APB1 * 2) feed so can get to 72 MHz (AHB), but none of the other peripherals are rated up there.

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    regmaster2
    regmaster2Author
    Associate II
    May 17, 2011
    Posted on May 17, 2011 at 14:19

    STOne-32?

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