It's a crazy idea to connect the AD9288BSTZ-100 at full speed to qspi.

[AVI-crak]

I know how to do it.

AD9288BSTZ has a 8bit parallel interface per channel. If you add a switch, you get ddr mode 4bit. If you use two channels qspi - then the data will be automatically placed in memory in the correct sequence 1-2-1-2-1-2. The theoretical speed of the external ADC interface will be 200 MHz, or 200M samples per second, or 100M for two separate ADC channels. Very beautifully it turns out. !!!

But I'm worried about the load on the processor itself, for it turns out 50M transactions per second 32bit words. What is 1/4 of the system bus capability. If you use the fifo dma, and transfer 4 blocks at once - that is, the probability of winning the bus arbitration by the time of recording.

A question about data bus arbitration from the dma side is how long does it take to wait for access to a packet write?

[Tesla DeLorean]

Wouldn't it just be easier to mash up some CPLD glue logic and interface via FSMC/DCMI, or using a AL422 / AL462

Honestly expect one would need some elasticity to manage contention/arbitration with data coming at high rates from fixed/hard clock, and different clock domains.

[S.Ma]

Signal integrity challenges and moving the data would add up bus bandwidth needs too.

[AVI-crak]

The qspi interface works as unusual as the sd card interface. He reads / writes at his speed until the moment of filling / emptying his FIFO block. And this unit is exactly two times larger than that of dma.

That is, the frequency of reading / writing data from qspi physics is stable, but you need to have time to process the buffer data.

Using FMC to read qspi does not make sense - it will add its own wait times.

You can use FMC to read the external ADC buffer, and you probably even need it. But this requires a fast memory fpga chip, and that is expensive. Much more expensive than the standard fast logic demultiplexer.

I have already checked the DCMI interface, it pulls 100MB maximum. In this case, the processor must operate at higher frequencies, and is always hot. The data received through the DCMI interface is always torn, there is no possibility to make line and frame synchronization equal to zero.