Is this an error in datasheet DocID15060 Rev 7 (STM32F103x4 STM32F103x6) - regarding SPI1_SCK when SPI_REMAP = 1.

[wb0gaz]

I was setting up pin assignments for a project and encountered a conflict between datasheet and reference manual. Can this be resolved?

The datasheet for STM32F103x4 STM32F103x6, filename stm32f103t4.pdf, dated 6/1/2015 9:41:55 AM appears to lack an entry for SPI1_SCK under SPI1_REMAP = 1.

According to RM0008 diagram 9.3.10 on page 181/1136, tSPI1_REMAP = 1 should connect SPI1_SCK to PB3.

In the datasheet Table 5 on page 28/99, PB3 Remap (right-most column) only includes TIM2_CH2 / PB3/ TRACESWO. PB4 and PB5 do include in the same column SPI1_MISO and SPI1_MOSI, so I suspect the reference manual should prevail.

Is there a way to confirm the possible error in the datasheet or otherwise resolve the apparent conflict?

Thanks

[wb0gaz]

(repeating unsolved issue raised 15-April-2022) ---

I am still looking for an answer to this question (regarding a discrepancy in documents describing available pin assignments for SPI1_SCK on STM32F103C6 series): Datasheet (June 2015 DocID15060 Rev 7) Table 5 PB3 shows Remap options of TIM2_CH2 /PB3/TRACESWO, while Reference manual (RM0008 Rev 21 181/1136) Table 56 shows PB3 as Remap option for SPI1_SCK. The part is evidently early enough generation that there is no "Alternate Function" mechanism (Remap was predecessor?) and therefore no corresponding alternate function tables in the datasheet.

As there wasn't any response to my original posting (15 April 2022), would you (reader) be able suggest how I could ask ST Microsystems support for clarification?

Thanks again for any help on this!

Dave

[waclawek.jan]

https://www.st.com/content/st_com/en/support/support-home.html

Don't hold your breath, though. Sometimes, the easiest and fastest way - even if not recommended - is to experiment. You can also try to have a look at "libraries" such as SPL and/or Cube; or click in CubeMX (I don't know if any of these is relevant for your case).

DS may prevail over RM in cases where RM addresses several models at once and the individual model has a deviation. Yes, it should say so.

You've already consulted the relevant Errata, I presume.

JW

PS. ST Microelectronics

[wb0gaz]

Your suggestion to try STM32CubeMX, (which I have been using to create simple test cases for peripherals I want to support "bare metal" style, but never considered as a tool for this question) seems like the most practical way to verify this, as those developers will presumably have based STM32CubeMX on authoritative documentation.

Thanks very much!

[wb0gaz]

The definitive answer to this was found in RM0008 Rev 21, page 186, section 9.4.2, about AF remap:

For AFIO_MAPR, Bit 0 (SPI1_REMAP), the authoritative text is:

Bit 0 SPI1_REMAP: SPI1 remapping

This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,

MOSI alternate functions on the GPIO ports.

0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)

1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)

I presume SCK/PB3 is absent in datasheet DocID15060 Rev 7 page 28 Table 5 due to document error.