Is there any advantage in the H7 SPI?

[Asantos]

Hi,

I would really like to understand why ST changed SPI on H7.

What can be done with SPIx->CR2.TSIZE? Is it possible to generate an ISR only after TSIZE bytes transfer?

Why 16 bytes FIFO? Is it possible to generate an ISR only after 16 bytes transfer, and in the ISR routine fill the FIFO with more bytes, if needed?

I noticed that the DMA transfer complet interrupt is generated before the SPI transmission ends, how can I get around this? This basically makes DMA transfer complete ISR useless.

[Jack Peacock_2]

The FIFO is to reduce bus cycles to SRAM. Look at the reference manual section on data packing with DMA. DMA performs four 32-bit bus accesses to load the FIFO, rather than sixteen byte wide accesses. That's more time available for other bus masters to access the same SRAM bank.

The FIFO can be used to buffer against underruns/overruns if running byte at a time interrupts, but DMA is so much simpler and more reliable it's not really a major improvement in that respect.

The early TX completion IRQ using TSIZE allows the application more setup time for the next block (e.g. locating next I2S audio block of data). If it's necessary to detect an empty FIFO, for example if another peripheral select is required, then the TXC interrupt can be used to guarantee a complete transmission, although since a TX is always followed by an RX all that's needed is to wait for the RX to complete. Far from being useless it's a nice feature when streaming data over SPI.

Jack Peacock

[Asantos]

Jack Peacock,

Thanks for your tip.

Now I realize that i have to setup one DMA channel to transmit and another DMA channel to receive and use the DMA receive channel ISR to know when all data has been transmitted. Even if the function is for transmission only. This way i won't need to setup the SPI EOT interrupt as HAL function does.

Ari.