I'm using the SPI peripheral on an STM32H743 as a slave. Is there a way to change the contents of the TX FIFO without resetting the peripheral? I need to always transmit a specifc byte at the beginning of a transaction along with other data, but the master may only request the first byte to analyze it (It is a status word indicating the repsonse is ready). At this point I need to refill the FIFO with the status word and the data.
Clearing and setting SPI_CR1_SPE when NSS goes high should do the trick. It does not reset the configuration.
Bit 0 SPE: serial peripheral enable
This bit is set by and cleared by software.
0: serial peripheral disabled.
1: serial peripheral enabled
When SPE=1, SPI data transfer is enabled, Configuration registers and IOLOCK bit in
SPI_CR1 are write protected. They can be changed only when SPE=0.
When SPI=0 any SPI operation is stopped and disabled, internal state machine is reseted, all
the FIFOs content is flushed, CRC calculation initialized, receive data register is read zero.
SPE cannot be set when MODF error flag is active.
You can configure an EXTI interrupt to be triggered on the NSS rising edge even when the pin is in AF mode, mapped to SPI. Then hope that the master always waits the time needed to run the handler before the next query.
There might be a way to automatize the process with the DMAMUX request generator, EXTI D3 pending clear registers. using one DMA channel to reset/set SPE, and another to refill the FIFO, but noone seems to have figured the request generator out yet.
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