Is it possible for slave to read on 1st clock edge and master to read on the 2nd clock edge for SPI?

[JAlle.2]

Upon reading the user manual for the STM32F072, it seems like it is only possible for the slave and master to both read on the first edge or both read on the second edge. However, I am trying to interface with an ASIC in which the ASIC(slave) reads on the 1st clock edge and the STM32 (master) reads on the 2nd clock edge. Is there any way to configure the SPI to work with this setup? The STM32 and ASIC are sending and receiving data at the same time so it seems like there is no way to send data first from the STM32, switch clock phase, and then receive data from the ASIC.

[TDK]

There's no way to do this if you want to transmit and receive simultaneously. If you do transmit and receive separately, you could swap the CPHA setting in between.

[JAlle.2]

Seems like the only thing I can do then is to bit bang it in software by toggling GPIOS and not use the SPI peripheral at all. Not ideal but the person who designed the ASIC created the slave SPI this way - I have to be able to communicate with it somehow simultaneously transmitting and receiving.

Thanks TDK for your quick response

[waclawek.jan]

I don't quite see why would be the STM32 constrained in which phase it uses, once it's master.

Post a diagram of the communication, please.

JW