Interrupt priority in STM32F1

[RezaMRBM]

Hello,

My question is that how many interrupts could be in pending state in STM32F1 MCUs? 

What would happen when a interrupt is running and in the same time another interrupt with same preempt priority be fired, does the running interrupt finishes and the second one be run or the first one should be finish and the next starts?

And my next question is that Assume that an interrupt is running and in this moment 2 or more interrupts with lower preempt priorities be fired. In this case two situations will occur:

1. Fired interrupts have the same preempt priority: Does the sub priority is determine the priority of interrupts?

2. Fired interrupts have different preempt priority: In this case does preempt priority determine the priority of interrupt execution?

Best regards

[TDK]

> My question is that how many interrupts could be in pending state in STM32F1 MCUs? 

Technically, all of them. Or at least all user interrupts, so something like 50.

> What would happen when a interrupt is running and in the same time another interrupt with same preempt priority be fired, does the running interrupt finishes and the second one be run or the first one should be finish and the next starts?

An interrupt can only pre-empt if it has a high priority than the currently executing interrupt. So it would finish, then the other would fire.

> 1. Fired interrupts have the same preempt priority: Does the sub priority is determine the priority of interrupts?

Yes, if it's defined. Otherwise, the numerically lower interrupt number fires first.

> 2. Fired interrupts have different preempt priority: In this case does preempt priority determine the priority of interrupt execution?

Yes.

[RezaMRBM]

Thank a million for your answer.

I got it.

Wishes the best

[RezaMRBM]

Hello,

Your previous answers solved my questions. Thank you for your favor. I have another question. How many interrupts with a higher preempt priority can occur successive? How many steps?

[TDK]

Question is a bit unclear. On the F4, there are 16 different preempt priority levels.

[RezaMRBM]

Thanks for your response

Assume that an interrupt is running and in this moment another interrupt with higher preempt priority be fired and the new interrupt begin to running. Again another interrupt with higher preempt priority be fired and like this many interrupts with higher interrupts will fire, in this case the previous interrupts will be left and the new one will be running.

my question is that, how many levels does it have this issue that running higher priority and start new interrupt? Does is have limitation?

for example if 3 times interrupts with higher preempt priority be fired and third interrupts is running, does the fourth interrupt with higher preempt priority would be fire or it will be lost?

I am going to know how many limitation is exist for firing and running interrupts for higher preempt priority.

[Piranha]

The priority levels depend on hardware implementation and the number of implemented bits are defined in CMSIS headers as __NVIC_PRIO_BITS.

Read this article:

https://community.arm.com/arm-community-blogs/b/embedded-blog/posts/cutting-through-the-confusion-with-arm-cortex-m-interrupt-priorities

And search for "Binary point" chapter in PM0056.

[RezaMRBM]

Thanks for your response

Assume that an interrupt is running and in this moment another interrupt with higher preempt priority be fired and the new interrupt begin to running. Again another interrupt with higher preempt priority be fired and like this many interrupts with higher interrupts will fire, in this case the previous interrupts will be left and the new one will be running.

my question is that, how many levels does it have this issue that running higher priority and start new interrupt? Does is have limitation?

for example if 3 times interrupts with higher preempt priority be fired and third interrupts is running, does the fourth interrupt with higher preempt priority would be fire or it will be lost?

I am going to know how many limitation is exist for firing and running interrupts for higher preempt priority.