Interrupt priority grouping field, NVIC_PriorityGroup

[obogush]

Posted on June 09, 2009 at 08:24

Interrupt priority grouping field, NVIC_PriorityGroup

[obogush]

Posted on May 17, 2011 at 12:16

Hi,

The description and number of NVIC_PriorityGroup constants in the firmware library does not match the PRIGROUP field description in the Cortexâ„¢-M3 Technical Reference Manual.

Is there a bug?

Thanks,

Olek

[artur2]

Posted on May 17, 2011 at 12:16

Hi,

At least for me it was a little confusing that ST naming (in that matter) is opposite to ''official'' ARM naming.

I mean that ST names priority group using number of bits assigned for preempt priority field and ARM uses names coming from exact value of PRIGROUP.

ST:

NVIC_PriorityGroup_0 - 0 bits for pre-emption priority 4 bits for subpriority, defined value of PRIGROUP 7

ARM:

PRIGROUP 7 - 0.8 indicates no pre-emption priority, eight bits of subpriority

Descriptions match but their names not.

Regards,

[obogush]

Posted on May 17, 2011 at 12:16

Dear STOne-32,

Thank you very much for your clarification. It is exactly what I was looking for. The UM0306 manual actually states that there are 16 programmable priority levels. However, it does not mention that only values from 7 to 3 are accepted by the PRIGROUP field in the Application Interrupt and Reset Control Register due to this limitation.

Thank you again.

Best regards,

Olek

[16-32micros]

Posted on May 17, 2011 at 12:16

Dear olek ,

Could you give more details what do you mean by does not match ?

The Cortexâ„¢-M3 Technical Reference Manual is a generic document from ARM implementing up to 241 external Interrupts in the micro & up to 8-bits of priorities.

In STM32F10x we have 43 external interrupts (different from the Cortex-M3 core) and only 16 levels (4-bit) of priorities are implemented. Which is enough to handle all the Interrupts priorities levels.

Implementing all bits is a waisting of the silicon area. ;)

Regards,

STOne-32.