Interrupt Nesting on STM32H745ZIT6: How many nested interrupts?

[KMand.1]

If there are more than three interrupts triggered simultaneously in the interrupt service routine/callback, how many nested interrupt the board can handle simultaneously. Or there are some cases of memory stack overflow which can lead to the dumping/skipping a low priority interrupt?

 

According to some blogs about ARM NVIC, it says it depends on the stack size. But I could not find a more precise answer or good literature regarding.

 

Looking forward to your answer.

 

Kind Regards,

Kishan

[Tesla DeLorean]

With the right settings on the NVIC it should permit 16 levels per core. You'd need enough stack for it to push each context, and the local/auto​ variables in each handler/call-tree.

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Although to hit these limits would suggest a highly dysfunctional approach to how much work each handler is doing in interrupt/callback context. That, or doing things at speeds that should be manged in HW, rather than SW.​

[KArum.2]

Hi @KMand.1​ 

STM32H745ZIT6 provide 16 interrupt priority level or each core but it allow 150 interrupts selection for each core.

Upto 16 line interrupt are designed. So you can use 16 ISR in simultaneously.