Interrupt mapping to NVIC ISR vector

[DCons.1]

I was looking at the ARM M7 reference manual, and it shows an empty NVIC ISR vector from 0x40 to 0x3fc. When I look at the file startup_stm32h725xx.s it defines specific interrupts mapped to the ISR vector. Are these hard mapped by the EXTI block and other blocks to these ISR vector locations or can the mapping be changed?

[waclawek.jan]

> Are these hard mapped

Yes, see NVIC chapter in RM.

JW

[DCons.1]

Thanks JW. Just realized I've seen that page before in RM0468. By my math there were 240 ISR locations in the Cortex M7 spec and only 162 positions used in the STM32H7 implementation. I wish ST had mapped the rest of the EXTI lines to discrete ISRs instead of EXTI9_5 and EXTI15_10.

[Tesla DeLorean]

The depth of the implementation is vendor specific, all the unused stuff being optimized out at a gate level.

The implementation does paint itself into corners at times, lot of the things in the STM32 family that get to be especially annoying with low-pin-count devices..

[waclawek.jan]

Here is a list of wishes for ST to ignore.

JW