Interfacing 8-bit DPRAM with STM32F407VGT6

[cwparker]

Posted on June 07, 2013 at 20:17

I need to interface the STM32F407 to a 1K x 8 DPRAM (7C131). The 100 pin STM32F407 package I want to use does not support nonmultiplexed address and data. I have no problem in using a latch to de-multiplex the A0-A7 from D0-D7, but the question is: ''is it valid in FSMC_BCRx to set MWID: 00, MTYP: 00 and MUXEN: 1''. The documentation says that MUXEN=1 is only valid for NOR and PSRAM memories. If it is not valid, would using MTYP of 01 or 10 (PSRAM or NOR Flash) be possible. I really don't want to use the 144 pin package unless it is the only option to interface to the DPRAM.

On another note, can the NBUSY output of the DPRAM be used as an input to NWAIT (setting ASYNCWAIT: 1 in FSMC_BCRx) to handle STM32 side collisions as a wait state?

[waclawek.jan]

Posted on June 10, 2013 at 11:11

While the FSMC documentation is, politely speaking, a mess; I am afraid that with multiplexed-address asynchronous memory you are left with Mode D only. Please review Fig.414 and Fig.415 if that fits the requirements of your memory.

> On another note, can the NBUSY output of the DPRAM be used as an input to NWAIT (setting ASYNCWAIT: 1 in FSMC_BCRx) to handle STM32 side collisions as a wait state?

I am no expert on dual-port  memories, but I am afraid the requirement to have NWAIT asserted 4 cycles before the transaction end might turn out to be a pain... or at least inconveninently slowing down the interface.

JW