Input pull-up to pull-down duration on STM32F303

[pmoore]

Posted on June 06, 2013 at 03:42

How long does it takes the STM32F303 to change an input from pull-up enabled to pull-down enabled? 

How long does it take to change an input from pull-up enabled to pull-down enabled?

It seems that if I read the input directly or shortly after changing the GPIO pull configuration, the input state is not stable...but I see the input line toggling between VDD and VSS on the scope (unless I pull it up or down externally with a few K ohms or less to VDD or VSS).

In this case the F303 is running at the maximum core and peripheral clock rates specified in the Rev 5 datasheet.  The clock source a very stable 8MHz TTL clock via the HSE input.

#stm32f3

[Tesla DeLorean]

Posted on June 06, 2013 at 04:12

In the hard sense, it depends on the pull up/down resistor (nominally 50K), and the capacitive loading on the pin. ie classic RC ramping.

From the core perspective the write buffer is going to add some latency from when the core dispatches the write and moves to the next instruction, and when the written value gets latched into the peripheral.

Your going to be able to change the pull up/down setting, and read back the current value very fast, ie sub micro second, likely a few hundred nano seconds.