Incorrect statement in STM32U3, STM32H5, STM32U5 docs
While looking at STM32U3C5 and STM32H503 datasheets I found incorrect information on ICACHE. Quote:
Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
The problem is: pseudoLRU may only be applied to 3- (or more) way set-associative caches. With 2-way set-associative, the single flip-flop per set provides true LRU and there is no such thing like “pseudoLRU” for 2 ways. You can’t do binary tree with a single flip-flop. PseudoLRU is normally used with 4 or more ways, since for 4 ways pseudoLRU requires 3 flip-flops organized as 2-level tree, with simple state transition logic while true LRU - 4 flip-flops and 12 states with much more complex state transition logic.
I suspect the same error might be present in all the STM32 documents describing MCU caches which are 2-way set-associative.