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Andreas Bolsch
Andreas Bolsch
Lead III
June 6, 2023
Solved

Inconsistency in WWDG_CFR description for STM32G0xx and STM32C0xx

RM0444 rev. 5, sec. 29.3.4 and RM0490 rev. 3, sec. 21.3.4 both employ only WDGTB[1:0], but WWDG_CFR description mentions WDGTB[2:0] with eight different prescaler settings. So actually two or three bits?

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Peter BENSCH
Peter BENSCHBest answer
ST Technical Moderator
June 6, 2023

Thank you for bringing this to our attention!

That indeed looks like a copy'n'paste typo. In fact, the time base of the WWDG has been extended compared to previous implementations and has three bits. The text strings WDGTB[1:0] still to be found in these RM should therefore be read as WDGTB[2:0].

Regards

/Peter

@Imen DAHMEN​ 

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2 replies

Peter BENSCH
Peter BENSCHBest answer
ST Technical Moderator
June 6, 2023

Thank you for bringing this to our attention!

That indeed looks like a copy'n'paste typo. In fact, the time base of the WWDG has been extended compared to previous implementations and has three bits. The text strings WDGTB[1:0] still to be found in these RM should therefore be read as WDGTB[2:0].

Regards

/Peter

@Imen DAHMEN​ 

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
Imen.D
ST Technical Moderator
June 6, 2023

Hello All,

Thank you for rising this up.

Internal ticket (ID 154205) is submitted to correct the typos in RM0444 and RM0490.

(PS: ID 154205 is an internal tracking number and is not accessible or usable by customers).

Imen

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