Imprecise Bus Faults and Write Buffer

[phani2]

Posted on August 18, 2011 at 15:58

Hi All,

Is there a way to disable the Write buffer on STM32F103xxx.

The Cortex M3 reference manual talks about ''

Auxiliary Control Registe

r'' which can be used to disable write buffer. Which will turn all imprecise bus faults to precise which means i will know the instruction which caused the fault and fix the code. But the ST Manual says this register is supported only in STM32F2 and L only.

I was wondering if there is any other way to disable write buffer. Or other ways to deal with Imprecise Bus Faults.

This fault happens randonmly and i dont know which specific instruction caused it.

Thanks in advance.

[Tesla DeLorean]

Posted on August 18, 2011 at 16:56

I don't have an immediate answer for the write buffer.

Look at the code around the fault, and the registers. It can't possibly be *that* far away from the offending write/store operation, and will be bracketed by any reads/loads.

Get a clear idea of the PC, LR, and the other registers, and the half dozen instructions prior. Use a fault handler to decode the state.

Check also your clocks, and the settings on the flash controller. Ideally demonstrate the problem running at 8-24 MHz

Do you have concurrent DMA running?

Is this occuring in interrupts?

[phani2]

Posted on August 18, 2011 at 17:26

Thanks for your response.

Yes i have a fault handler and I log ( over the serial port ) the fault and the associated registers. The Program Counter always points to a CMP instruction, this fault occurs in RTX OS call os_mbx_wait. I am using the Keil RTX RTOS. I have debugged the code around mailbox send and receive and didn't find anything suspicious. Thats what makes me wonder if the stacked PC is the cause of the fault.

But you are right the stacked PC should not be very far from the instruction which caused the fault, let me probe down this line.

[joseph239955_st]

Posted on August 19, 2011 at 00:55

Maybe you can try to use the MPU to program the memory space as non bufferable? This should be able to disable the write buffer.

Note: it will slow things down.

The auxiliary control register was added in Cortex-M3 rev 2. Note that if there are additional write buffers in the system bus (e.g. at bus bridge), the auxiliary control register will not be able to disable those.

[Nickname12657_O]

Posted on August 19, 2011 at 23:27

Hi,

STM32F103xx is using Cortex-M3 r1p1 revision  and only STM32F103 ( XL-density) : 768 and 1024Kbytes versions of embedded Flash  has MPU.

Cheers,

STOne-32.