Impedance control for high speed SPI

[sagan]

Hello,

We are a company making medical air transport containers. We use ST micro-controllers (STM32L562ZET6Q) to track, monitor and control our containers around the world.

We are having issues with signal integrity between our micro-controller and our memory IC (MX25L25645GZNI-08G - SPI) on our PCBs. With the same layout (we only changed connectors that are far away from the memory) we have a worse signal integrity on the latest batch than on our first one. But both signals on the clock line look bad at 13MHz. The uC and memory are close (15 mm) and the data and clock lines are quite straight and do not change layer. At 13MHz, the signal integrity gets so bad that we start to have reading / writing issues, especially at high temperatures (> 55°C). For now, we just use a safe speed of around 3MHz on the clock line. What are your recommendations about impedance control / matching ? Do you have any design guidelines for a high speed SPI interface on these micro-controllers ? I am not very experienced on this subject.

Some oscilloscope captures below:

Thanks in advance for your help on this matter.

[LCE]

I hope you are not using CubeMX / HAL stuff for these functions?

Anyway, check if your GPIO settings (speed) have changed.

At 3 MHz / 13 MHz I can't really imagine that it is a PCB / layout issue, especially if the lines are really as straight and short as you told us.
Unless you have changed the layout? Maybe no ground plane below thee traces?

What about the other signals? Do they show the same level of degradation on the new PCBs?

[Tesla DeLorean]

What actually changed?

The batch/source of the MCU or the memory IC's? Different PCB?

Do the MCU come from a different assembly plant or use a different stepping of the IC?

The GPIO slew rate control is via GPIO SPEEDR settings, should perhaps have a look at those in a loading / length context rather than purely speed in MHz.

I suspect the QSPI device might also have configurable speed / loading settings for the IO's

Anything remarkable about the clock trace, or grounding? Two layer board? Good probe points?

[Tesla DeLorean]

https://www.mxic.com.tw/Lists/Datasheet/Attachments/8906/MX25L25645G,%203V,%20256Mb,%20v2.0.pdf

Check Output Drive Strength settings, probably not applicable to clocking admittedly.

Show PCB / Schematic for salient signal paths.

[Piranha]

Could be the famous ignorance of the required delay after enabling the peripheral clocks. For example, while the clock is not effectively enabled, a write to GPIO_SPEEDR register is ignored. Not only ST's broken bloatware ignores it, but 99% of the code I've seen ignores it.