I2S swapped L/R channels after I2SResume

[akosodry]

Posted on February 06, 2017 at 23:24

Hello,

I collect the ADC data through the I2S1 peripheral using DMA2

Once

1) i collected certain amount of results,

2) the reception is paused with:

HAL_I2S_DMAPause(&hi2s1);

3) I send the data through UART

4) then the reception is resumed with:

HAL_I2S_DMAResume(&hi2s1);

then this mechanism can be started again from point 1).

What i observed is that somehow (not always, but ~8/10 times) the L and R channels have been swapped. I attached a figure of the results.

(I inferred on the swapping based on that the ADC sends ch1 and ch2 results one after another, and the voltage on ch1 is approximately 10 times bigger then on ch2)

Is there anyone who could give me a tip what is the problem?

Thank you very much in advance.

Best regards.

#stm32-i2s-dma #programming-i2s #i2s-dma #stm32-i2s #i2s-channel-side-issue #i2s

[waclawek.jan]

Posted on February 07, 2017 at 00:42

I don't know what is your target mcu, but I looked into the F4 Cube's HAL_I2S_DMAResume() and it's barely more than simply setting the DMA-enable flags in I2S. There's no LR-sync mechanism in that; as the Rx flag is surely already set, DMA will immediately transfer whatever it finds in the data register, and then all subsequent data.

Generally, it's a bad idea to try to pause I2S. Stop it completely if you must, and then restart. Or, better, devise a scheme which does not require to stop I2S to be able to pick some of the data and transmit through USART (e.g. using double-buffer DMA, and redirecting the buffers to another buffer-pair).

JW

[akosodry]

Posted on February 07, 2017 at 13:16

Thank you for your response.

But. Does the HAL_I2S_Receive_DMA function have the LR-sync mechanis??. I mean.

First) i setup the MCO and PLL

Second) i setup the I2S with HAL_I2S_Init which produces stable LR clock

Third) i initialize the ADC

Fourth) i have other peripherals to be set up, and also some calculations and just then in the

Fifth step) i call the HAL_I2S_Receive_DMA function.

Will the 

HAL_I2S_Receive_DMA sync the DMA with L/R clock? e.g. following the aforementioned step will the array (that the dma fills) be well ordered (ch1-ch2-ch1-ch2-ch1-ch2....) or could the swapping happen?

Thanks a lot in advance.

[waclawek.jan]

Posted on February 07, 2017 at 13:54

I don't Cube and I won't investigate it, sorry. You can look it up yourselves, the sources are open.

Note, that particular device and whether it's used as slave or master may make difference in determining what's the proper method of synchronization, see e.g. STM32F40x errata rev.8, erratum 2.6.1.

JW