I2S ''R Division Factor''???

[Terence D]

Posted on September 25, 2017 at 22:12

Hi - I'm trying to configure my STM32F429 Discovery board to send digital audio data to a

http://store.digilentinc.com/pmod-i2s-stereo-audio-output/

.  Section 28.4.4 (pg 911) of the

http://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf

says:

To achieve high-quality audio performance, the I2SxCLK clock source can be either the PLLI2S output (through R division factor) or an external clock (mapped to I2S_CKIN pin).

I can't find any other mention (let alone an explanation) of what this 'R division factor' is.  Does anyone know what this means?

-Terence

#stm32f4 #i2s

[waclawek.jan]

Posted on September 25, 2017 at 22:25

JW

[Tesla DeLorean]

Posted on September 25, 2017 at 22:26

Each PLL has three divider taps for the VCO, P, Q and R. On the main one the P one goes to the processor, the Q to USB/SDIO.

Say you run the VCO at 360 MHz, a P setting of 2 gets you to 180 MHz.

[Terence D]

Posted on September 25, 2017 at 22:46

Ah, got it, thanks! Makes perfect sense after showing it to me on the clock tree diagram.