I2S MCLK runs too fast!

[jensen006]

Posted on June 07, 2010 at 16:01

I2S MCLK runs too fast!

#programming-i2s

[jensen006]

Posted on May 17, 2011 at 13:54

Hi Clive

I do get the right SYSCLK and using the clock divider I can make it 36Mhz. The problem is a the I2S master clock output doesn't show to be 12.8Mhz (48e3*256) but 25Mhz. I suspect that this has to do with the I2S configuration.

I understand if this thread it getting boring :)

Thanks again

Thomas

[drzile86]

Posted on May 17, 2011 at 13:54

I work with STM32F107RC and codec CS42L51. I configure and set up all for I2S2 communication, but MCLK signal on PC6 pin is only present when I send data over I2S2 in interrupt subroutine. I need MCLK signal all time. 

Is MCLK only present when you send data?

Dragan

[chikos332]

Posted on May 17, 2011 at 13:54

That's how the I2S works on STM32: MCLK and all I2S clocks are generated only when you send data.

I used the CS43L22 and I did simply send dummy data when I have no real data to send (note: using DMA is much more performant than using interrupt).

I also tried without sending dummy data and it works as well (you just have to set mute before end of streamand reset it again before restarting a new stream).

Third solution: you can use an external clock for both I2S and CS42L51 and use I2S in slave mode.

Anyway, have a look on the USB audio speaker which is using the audio codec and the I2S:

http://www.st.com/stonline/products/support/micro/files/um0424.zip

[drzile86]

Posted on May 17, 2011 at 13:54

Thanks, Chikos 

I will try with first and second solution... 

Best regards,

Dragan