I2S Interrupt and Optimisation

[martinmartin9129]

Posted on September 10, 2013 at 17:02

Hello All.

In my app. I have I2S Transmitter with External Clock.

I want to test the clock frequency.

At clocktest.c I make:

[code]

volatile u32 clknum;

extern volatile u32 SendTmr;

void ClockTest(void){

     Delay(10);

     SendTmr=0;

     Delay(100);

     clknum = SendTmr;

}

[/code]

and in stm32f4xx_it.c I make:

[code]

volatile u32 SendTmr;

//

void SPI3_IRQHandler(void){

volatile static u32 status;

 

  status = SPI3->SR;

  SPI3->DR = 0;

  SendTmr++;

}

[/code]

Global optimisation settings:  Level2, Optimise for time.

All works fine, if I set localy for stm32f4xx_it.c: no ''optimise for time'' and Level0.

If I use global settings to this file - I gen the wrong number in SendTmr and also in clknum.

But, if I add test_pin_toggle() at the end of interrupt subrotine all works fine with optimisation global settng.

[code]

volatile u32 SendTmr;

//

void SPI3_IRQHandler(void){

volatile static u32 status;

 

  status = SPI3->SR;

  SPI3->DR = 0;

  SendTmr++;

 test_pin_toggle();

}

[/code]

I can leave pin toggle forever, but it is not a good idea, because I don't understand what happened.

What to do?

Thank you.

#i2s-spi-interrupts-interrupt-isr #stm32

[waclawek.jan]

Posted on September 10, 2013 at 22:17

> If I use global settings to this file - I gen the wrong number in SendTmr and also in clknum.

Roughly twice the expected value? Then the interrupt succeeds to fire again (tailchains) during the ISR exit due to delays between the SPI status bit clear - to - NVIC input detect.

Increment SendTmr only if TXE bit in status register is set.

Better perhaps, check for TXE cleared before exiting the ISR.

JW

[martinmartin9129]

Posted on September 11, 2013 at 10:25

Great!

You are right!

Waiting for TXE==0 at the end of ISR totally solve the problem.

Many thanks!