I2C Multimaster: Distinguish Idle from Clock-Stretch Timeout

[flyer31]

Hi,

is there some clear method for the ERRIE TIMEOUT interrupt to be sure, that the IDLE condition is causing the interrupt?

(I need the Idle interrupt in a multimaster system to start Transmit...)

(I also need to enable the TEXTEN in TIMEOUT register, so that the clock stretch will finish after maximum 1 byte cycle... (NOSTRETCH=1 is not possible for Master appliction... typically clock stretch cannot appear in my application when sending, but in some error condition I am frightened it COULD appear ... e.g. it appears if the DMA module somehow does not work or has some delay... usually I setup all correctly and Reset the DMA full flags before starting DMA, so all SHOULD run fine, but who knows that "run fine" will run fine ALWAYS?)

Unfortuanately IDLE condition and Clock Stretch Timeout condition both set the same ISR interrupt flag TIMEOUT... .

[Danish1]

Could you look at the SCL and SDA lines?

If there's a clock stretch timeout, it implies that some external device is keeping SCL low.

Whereas when idle, SCL and SDA are both high.

Of course the interrupt handler has to check this sufficiently quickly - before the external device stops pulling SCL down.

As I understand I2C, original intention was for masters intending to transmit to wait for a stop-condition on the bus if they found it busy. And busy-detection is something that stm32 hardware supports.

Hope this helps,

Danish

[flyer31]

Thank you for answer.

But this I tried already. The Master will e. g. hold down SCL by himself and then release SCL and fire this TIMEOUT interrupt... but it looks like in this case the SCL is already High again, when the Interrupt arrives... . So this unfortunately does not work... .