I2C clock stretching in master mode and other I2C issues

[DiBosco]

Posted on July 15, 2010 at 17:13

I2C clock stretching in master mode and other I2C issues

[greg_t]

Posted on May 17, 2011 at 13:58

Hello,

Clock streching is used by slow slaves .. If your slave perform some calculations or other tasks with the recieved data on I2C it holds the clock low until finished proccesing the data (may be interrupt routine ). After releasing the clock the Master may send another byte of data .....

[DiBosco]

Posted on May 17, 2011 at 13:58

@Gregory, thanks for the clarification.

@Crossware, thanks for that, I shall implement that for if/when it gets stuck.

I found an error on the layout of the Atmel chip which seems to have helped a lot as well.

[stforum2]

Posted on May 17, 2011 at 13:58

We found it necessary to reset the I2C (in order to clear the busy bit if I recall):

    g_pRCC->APB1ENR |= I2C1EN;

    g_pI2C1->CR1 = I2C_SWRST;

    g_pI2C1->CR1 = 0;

    g_pI2C1->CCR = I2C_CCR7 | I2C_CCR5;

    g_pI2C1->TRISE = 0X09;

    g_pI2C1->CR2 = I2C_FREQ5;

    g_pI2C1->CR1 = I2C_PE;