I want to get gpio clock by passing data into GPIO_BSRR registers by DMA transaction on capture compare timer event. It doesn't work.

[MBelk]

My timer config:

  RCC_APB1ENR = RCC_APB1ENR_TIM3EN;

  TIM3_CR1 = (uint32_t)(TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_CENTER_3);

  TIM3_CR1 &= ~TIM_CR1_UDIS;

  TIM3_CR2 &= ~TIM_CR2_CCDS;

  TIM3_ARR = (uint32_t)10000;

  TIM3_DIER = (uint32_t)(TIM_DIER_CC1DE | TIM_DIER_CC1IE);

  PWM_BORDER = (uint32_t)7000;

So, timer interrupt is working well only when I null CCR event in the interupt.

But transaction interrupt arises at random moments of time. While transacion must takes few SysClk's. May be I have wrong timer config of timer or wrong DMA channel?

DMA config:

  RCC_AHBENR |= RCC_AHBENR_DMA1EN;

  DMA1_CPAR4 = (uint32_t) &GPIOF_BSRR;

  DMA1_CMAR4 = (uint32_t) &clockSeq;

  DMA1_CNDTR4 = (uint32_t) 4;

  uint32_t ccr = DMA_CCR_MINC | DMA_CCR_MSIZE_16BIT | DMA_CCR_PSIZE_16BIT;

  ccr |= DMA_CCR_PL_VERY_HIGH | DMA_CCR_DIR | DMA_CCR_CIRC;

  ccr |= DMA_CCR_HTIE | DMA_CCR_TCIE | DMA_CCR_TEIE;

  DMA1_CCR4 = ccr;

As said earlier, I have interrupt at wrong moments of CLK

void dma1_channel4_7_dma2_channel3_5_isr()

{

//  TIM3_SR &= ~TIM_SR_CC1IF;

  static int cnt = 0;

  timDump[cnt++] = TIM3_CNT;

  if(cnt == 50) cnt = 0;

}

timDump = 3817, 3913, 4009, 4105, 4201 ...

stm32f030f4p6 MCU.

[Tesla DeLorean]

BSRR should be 32-bit wide

ARR = N-1 for Divide by N

CNT will be zero at update event, and thus DMA HT/TC IRQs

TIM3_UP is channel 3 on the DMA, not 4

[MBelk]

Thank you, but I want to clock on compare event, not update

[Tesla DeLorean]

For Channel 4 (TIM3_CH1), you'd need to configure TIM3->CCR1 and enable it

[waclawek.jan]

Read out and check/post content of relevant TIM and DMA registers.

JW

[MBelk]

checked

[waclawek.jan]

And did you find the problem?

Do you check and clear the DMA status flag which causes the DMA ISR to be invoked?

JW

[MBelk]

checked