I've got a very strange situation on my STM32G0B0VE GPIO pin A8 gets to be the inverted signal of what PA9 is (it doesn't matter what PA9 is it can be output or Tx of Uaert1). I've checked the errata sheets. See details for more information...

[SCous.1]

I've made a software so small that it does only the following steps:

1) init clock and everything to work.

2) in the main program I set PIN GPIO_A_8 to input with pull up enabled, nothing is connected to that pin except for a scope probe.

3) then I configure PA9 to GPIO push-pull, here also nothing connected but a scope probe.

4) a small task that sets GPIO_A_9 to high and to low with a dutycycle of 50% and every 100ms.

5) on my scope image i see that pin PA8 follows pin PA9 but inverse output, so when PA9 goes up, PA8 goes down to 400mV, when PA9 goes down to ground level, PA8 goes to 3V3.

I can't seem to figure out what I'm doing wrong here and why PA8 starts to inverse following PA9. If I switch PA8 and PA9 (driving PA8) Then PA9 does not do anything strange and stays 3v3.

I also do not think I have a short as the signal would never be inverted....

If any of you have any idea what to do it would be appreciated. This is very strange at least.

[Antoine Odonne]

Hello,

Could you please check if strobbing the UCPD1_STROBE bit at the very beginning of your code execution has an effect here?

clock first SYSCFG bloc... More details here below, cf RM0454

Bit 9 UCPD1_STROBE: PB15 and PA8 pull-down configuration strobe

Upon power on, internal pull-down resistors on PB15 and PA8 pins are enabled (connected).

Setting this bit disables (disconnects) the internal pull-down resistors.

Thank you and regards,

Antoine

[SCous.1]

Hi, Indeed this was what was needed. I was not expecting that behavior for a pull down resistor. But I've added the following lines before configuring my clock:

 // disable strobe for UCPD1 and UCPD2 
 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UCPD1_STROBE_Msk);
 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UCPD2_STROBE_Msk);

And that did the trick.

Thanks For the quick response, It saved me a lot of problems.

Kind regards

Coussement Stijn

[waclawek.jan]

Hi @Antoine Odonne​ ,

this, and all similar related problems, is a recurring theme here ever since the 'G0 appeared.

Why don't you add a footnote to the pin table in DS for *all* 'G0 *and* 'G4, explaining this issue; and the same to the GPIO chapter in related RMs? That's where most of the users search for information when this sort of problem occurs, and the pin table in DS is the place where users would/should find this information even before they start designing.

Thanks,

JW

[SCous.1]

I can only support such initiative as I would have never guessed to check the SYSCFG register for a pin that doesn't even mention this in the GPIO chapter. It would have made it even easier than find help online.

What was specifically confusing what the behavior of PA8 that followed PA9. If it would only stay at 0.4V we would have maybe searched the RM for pull down. But we where so confused here...:grinning_face_with_sweat: