I'm Trying to Enable SDRAM without STM32 Library. But Not works.

[mymy49]

Posted on June 25, 2015 at 07:36

The original post was too long to process during our migration. Please click on the attachment to read the original post.

[Tesla DeLorean]

Posted on June 25, 2015 at 15:07

Suggest you take the SPL code that does the configuration properly and bisect against yours until you understand which piece is ''not working''.

[mymy49]

Posted on June 25, 2015 at 17:11

dear clive1.

thank you your reply.

I was Trying to compare with STM32 Library.

I think, This source code is almost same configuration process with STM32 Library.

I am confused.

[mymy49]

Posted on June 25, 2015 at 17:13

I was Attached all source code Files now.

[Mark Edwards]

Posted on June 25, 2015 at 20:48

That looks very complicated. This works for STM32F429 Discovery board.

void SDRAM_Init (void) {
uint32_t temp32;
/* GPIO configuration for FMC SDRAM bank */
/*
+-------------------+--------------------+--------------------+--------------------+
+ SDRAM pins assignment +
+-------------------+--------------------+--------------------+--------------------+
| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | <<<
NEW
for 64MB
| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG8 <-> FMC_SDCLK |
| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 | PG15 <-> FMC_NCAS | 
| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |--------------------+ 
| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | 
+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | 
| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | 
| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
+-------------------+--------------------+--------------------+
| PB5 <-> FMC_SDCKE1| 
| PB6 <-> FMC_SDNE1 | 
| PC0 <-> FMC_SDNWE |
+-------------------+ 
*/
// GPIOB Configuration - PB.6&5
GPIOB->MODER = GPIOB->MODER | 0x2800; // Alt Fn
GPIOB->OSPEEDR = GPIOB->OSPEEDR | 0x2800; // 50MHz
GPIOB->AFR[0] = GPIOB->AFR[0] | 0x0CC00000; // SDRAM
// GPIOC Configuration - PC.0
GPIOC->MODER = GPIOC->MODER | 0x2; // Alt Fn
GPIOC->OSPEEDR = GPIOC->OSPEEDR | 0x2; // 50MHz
GPIOC->AFR[0] = GPIOC->AFR[0] | 0xC; // SDRAM
// GPIOD Configuration - PD.15,14,10,9,8,1,0
GPIOD->MODER = GPIOD->MODER | 0xA02A000A; // Alt Fn
GPIOD->OSPEEDR = GPIOD->OSPEEDR | 0xA02A000A; // 50MHz
GPIOD->AFR[0] = GPIOD->AFR[0] | 0xCC; // SDRAM AFRL
GPIOD->AFR[1] = GPIOD->AFR[1] | 0xCC000CCC; // SDRAM AFRH
// GPIOE Configuration - PE.15,14,13,12,11,10,9,8,7,1,0
GPIOE->MODER = GPIOE->MODER | 0xAAAA800A; // Alt Fn
GPIOE->OSPEEDR = GPIOE->OSPEEDR | 0xAAAA800A; // 50MHz
GPIOE->AFR[0] = GPIOE->AFR[0] | 0xC00000CC; // SDRAM AFRL
GPIOE->AFR[1] = GPIOE->AFR[1] | 0xCCCCCCCC; // SDRAM AFRH
// GPIOF Configuration - PE.15,14,13,12,11,5,4,3,2,1,0
GPIOF->MODER = GPIOF->MODER | 0xAA800AAA; // Alt Fn
GPIOF->OSPEEDR = GPIOF->OSPEEDR | 0xAA800AAA; // 50MHz
GPIOF->AFR[0] = GPIOF->AFR[0] | 0xCCCCCC; // SDRAM AFRL
GPIOF->AFR[1] = GPIOF->AFR[1] | 0xCCCCC000; // SDRAM AFRH
// >>>OLD PRE A12 - 64MB SDRAM
// // GPIOG Configuration - PG.15,8,5,4,1,0
// GPIOG->MODER = GPIOG->MODER | 0x80020A0A; // Alt Fn
// GPIOG->OSPEEDR = GPIOG->OSPEEDR | 0x80020A2A; // 50MHz
// GPIOG->AFR[0] = GPIOG->AFR[0] | 0xCC00CC; // SDRAM AFRL
// GPIOG->AFR[1] = GPIOG->AFR[1] | 0xC000000C; // SDRAM AFRH
// GPIOG Configuration - PG.15,8,5,4,2,1,0 >>>NEW A12<<<
GPIOG-
>MODER = GPIOG->MODER | 0x80020A2A; // Alt Fn
GPIOG->OSPEEDR = GPIOG->OSPEEDR | 0x80020A2A; // 50MHz
GPIOG->AFR[0] = GPIOG->AFR[0] | 0xCC0CCC; // SDRAM AFRL
GPIOG->AFR[1] = GPIOG->AFR[1] | 0xC000000C; // SDRAM AFRH
// Enable Peripheral Clock
RCC->AHB3ENR = RCC->AHB3ENR | 0x1; // Enable FMC
// FMC SDRAM bank initialization
FMC_Bank5_6->SDCR[0] = 0x2800;
FMC_Bank5_6->SDCR[1] = 0x1D4; //>>>Old 4MB SDRAM<<<
// 
FMC_Bank5_6-
>SDCR[1] = 0x1DB; // 64MB Device
FMC_Bank5_6->SDTR[0] = 0x106000;
FMC_Bank5_6->SDTR[1] = 0x10361;
// FMC SDRAM device initialisation sequence 
// Configure a clock configuration enable command
while (FMC_Bank5_6->SDSR & 0x20) { // Controller not ready for new request
};
FMC_Bank5_6->SDCMR = 0x9; // Send Command
//need 100ms delay
for (temp32 = 0x00; temp32 < 
0xD0000
; temp32++)
{
temp32
= temp32;
}
// Configure a PALL (precharge all) command
while (FMC_Bank5_6->SDSR & 0x20) { // Controller not ready for new request
};
FMC_Bank5_6->SDCMR = 0xA; // Send Command
// Configure a Auto-Refresh command
while (FMC_Bank5_6->SDSR & 0x20) { // Controller not ready for new request
};
FMC_Bank5_6->SDCMR = 0x6B; // Send First Command
while (FMC_Bank5_6->SDSR & 0x20) { // Controller not ready for new request
};
FMC_Bank5_6->SDCMR = 0x6B; // Send Second Command
// Configure a load Mode register command
while (FMC_Bank5_6->SDSR & 0x20) { // Controller not ready for new request
};
FMC_Bank5_6->SDCMR = 0x4620C; // Send Command
// Set the refresh rate counter
FMC_Bank5_6->SDRTR = 0x556;
while (FMC_Bank5_6->SDSR & 0x20) { // Controller not ready for new request
};
/* Disable write protection */
temp32 = FMC_Bank5_6->SDCR[0]; 
FMC_Bank5_6->SDCR[0] = (temp32 & 0xFFFFFDFF);
}