I get an ADC overrun with multimode, scan and timer-triggered configuration

[JGant.1]

I'm using the STM32F446VE with 3 ADCs. I have a 50 kHz PWM running and want 2 of the ADCs to measure 2 Channels synchronized with the 50 kHz PWM.

To achive this I used the regular simultanuous dual mode, and triggered the master ADC with the Trigger 8 Timer Out event, which runs at 50 kHz (by now I assume this doesn't make sense, as I could just trigger both ADCs with the timer 8 and have synchronous measurement, as long as they have the same sampling time, but I'd like to understand what went wrong anyways). Both ADCs have Scan Conversion enabled.

Now, as soon as the total ADC Conversion takes too long, I get an ADC Overrun. This can be achieved by reducing the Sampling Time, Resolution, Delay, or clock Prescaler. I get the same behaviour when I raise the Timer 8 Frequency.

What I find very odd is, that the overrun does not accur, when I make the ADC Conversion ver slow, for example by raising the Sampling Time to 480 Cycles, or raise the Prescaler to 8. Shouldn't I get an overrun exactly then, because the Conversion is slower than 50 kHz and therefore gets retriggered, before it is done?

So, why do I get an ADC overrun Problem with the code, I added below?

Why do I not get an ADC overrun Problem, when the whole ADC conversion takes a lot of time?

Am I right, that triggering both ADCs with the same timer should get me the results I wish to have?

I have added the code which does not work. As I've said, if I change for example the ADC Clock Prescaler to 8, it seems to work just fine.

[TDK]

Overrun happens when the ADC converts a new channel without the previous one being shifted out via DMA. Slowing down the clock gives the DMA more time to do its job which avoids the overrun. Enabling the FIFO can mitigate this problem.

Overrun does not occur if you retrigger the conversion without the previous one being complete. That's not what an overrun is here.

Triggering both ADCs with the same timer seems like a good solution to get the values at the same time.

[JGant.1]

Thanks for your reply! This explains why making the ADC conversion slower does not generate an overrun.

Why would a FIFO help here? I always thought without FIFO the DMA just overwrites the old values, which is the behaviour I want. I don't care about old values and only want the latest one.

Does this also mean, that the DMA ist just too slow, to get the ADC values in time? That would surprise me, I tested different configurations where the ADCs where running a lot faster and I didn't have a Problem.

I don't get the problem when I have 2 independent channels triggered by the same timer with a way faster configuration (prescaler set to 2, sampling cycles set to 3,...)

[TDK]

If you only want the latest value, and you're only converting one channel per ADC, don't use DMA. Just disable overrun detection and read the ADCx->DR register directly when you need it.

[JGant.1]

I'm measuring 2 channels per ADC, this is why I am using the DMA. But I want channel 1 of ADC 1 to be synchronized with the channel 1 of ADC 2, same with the channel 2.