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AGipe.1
Associate
February 6, 2020
Question

I am trying to process video signal from a linear CCD, is it possible to add two stop bits to the end of the digital output signal?

  • February 6, 2020
  • 3 replies
  • 1216 views

I am looking at options to replace my mostly obsolete design using an FPGA and old linear CCDs. I've already chosen a new linear CCD chip but I'm considering a handful of processing options. Our CCD alignment system currently uses 13 bits output to our processor box, with two of those bits being stop bits (0 and 1). Can this microcontroller tack on stop bits to my digital output signal? If it matters, our digital output is running as NOT output (a 0 is 1V, a 1 is 0V).

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    3 replies

    waclawek.jan
    Super User
    February 6, 2020

    Tell us more, what signal are you talking about - synchronous, asynchronous, clocks are generated from where?

    A simple schematic diagram and a waveform sketch would help.

    JW

    AGipe.1
    AGipe.1Author
    Associate
    February 7, 2020

    See below for more info. I accidentally replied incorrectly I think. I'm new to the forums.

    AGipe.1
    AGipe.1Author
    Associate
    February 6, 2020

    Synchronous. Clocks are currently generated from our FPGA, passed through a couple video driver ICs and load resistors mostly just to condition the pulse amplitude to what the CCD needs. Using a 20MHz crystal for master. See below for an example of the output signal I need to send to the controller box. High is 0, low is 1, each bit is roughly 2.2us width, the final 0 and 1 are the stop bits and are added after ADC conversion in our FPGA before it spits out the signal. This image is the final conditioned signal after a transistor and a couple resistors.0690X00000D8EJoQAN.jpg

    waclawek.jan
    Super User
    February 10, 2020

    I still don't quite understand what are you trying to accomplish, but generally, newer STM32 models' SPI can select any data size between 4 and 16 - that should perhaps fit your application.

    JW

    AGipe.1
    AGipe.1Author
    Associate
    February 12, 2020

    I'm not worried about the bit count. So in the picture above, our controller would read these bits right to left as they are streamed in. The final two bits (a 0 followed by a 1) are not part of the data count but are added by our FPGA as part of the signal to the controller to stop reading. Is the STM32 capable of adding bits in it's logical output? I'm unfamiliar with microcontrollers as a whole and was wondering if this capability exists.