I am looking the STM32L443CC Datasheet (DS11421 Rev 5 October 2019) and trying to figure out how you come up with the values for Table 66 Rain.
Doing my due diligence, I did find someone else asked the question in 2019 but there was no response.
https://community.st.com/s/feed/0D50X0000BaM9PoSQK?t=1669134764953
What it did show was the equation, but not where he found it, and no description of the variables.
I am guessing CADC is the capacitance of the ADC. Which I am guessing is in Farads, and the datasheet says it is 5 pF.
I am also guessing that N is the number of bits of Resolution, which is 12 in my case. But I do not understand why there is 2 added to it.
Is fADC the clock frequency of the ADC? The table uses 80 MHz
I am guessing RADC is the internal ADC resistance. which is not specified in the datasheet like the capacitance is.
Then there is k. Which I am guessing is sampling time. Do they take off the .5 to make it maximum? Seems like the wrong direction.
In any case it does not work. Also the datasheet does not specify the difference between the fast and slow channels. What is different in the HW?
