HSI48 vs PLL as USB clock

[alessandro.breuza]

After weeks of debugging TXERR on USB host, I figured out that changing OTG clock from PLL3Q to HSI48 errors disappear.

STM32H733 running at 336MHz from HSE @25MHz. USB connected to an LTE modem (CDC ECM).

 

With few tasks and interrupts errors occur at an average rate of 1/minute, but under heavy load (30+ tasks and 5 TIM interrupts <1ms) the error rate rises to 20/minute ca.

As said, using HSI48 errors completely disappear under any condition.

 

Is HSI48 more stable than PLL? How does CPU load influence PLL?

 

Alessandro

[AScha.3]

HSI is quite bad in terms of jitter, as its just a RC oscillator. (see ds for jitter values)

PLL should be much better, if source is a crystal /osc. Its the golden standard for stable clocks.

Just check: no fractional setting (frac = 0) and no Spread Spectrum Clocking (SSC) is activated.

CPU load has no influence on PLL. (except your power supply/decoupling is so bad, the VDD gets modulated.) 

[alessandro.breuza]

I totally agree with you, but evidence shows the opposite…

I confirm no fractional divider and my MCU does not support SSC.

[Gyessine]

Hello ​@alessandro.breuza 

The PLL + HSE clock should be more stable than HSI48, especially for a host application.

The fact that your application behaves more smoothly with HSI48 suggests that the issue might come from another source.

The issue might be related to hardware or to the clock configuration.

Can more details about the project be shared?
BR
Gyessine

[alessandro.breuza]

This is the ioc of the project

[Gyessine]

Hello ​@alessandro.breuza 
I reviewed the .ioc  file.

With a project as complex as this, an in-depth debug process is required to identify the root cause. To avoid synchronization issues or conflicts between multiple peripherals and middleware components, start by creating a new minimalist project that implements only the USB CDC ECM functionality. Then check whether the same issue still occurs.
Waiting for your feedback
Gyessine

[alessandro.breuza]

Disabling (almost) all interrupts and the majority of tasks the error rate reduces drastically.

CPU-intensive tasks (such as SSL cloud connection manager) increase occurrences.

On the other hand, error rate decreases when USB IRQs and tasks have maximum priority.

 

Alessandro

[Pavel A.]

Just to add a $.01 to previous replies: The RTOS and software issues such as number of tasks, interrupt handling do matter, but these are not the root cause in this case, so focusing on the hardware. The main difference between HSI48 and PLL is obviously internal vs external source. On custom boards, quality of external clock can suffer from improper capacitors and so on. Seen it more than once on STM32 and other SoCs. You can route sysclk (divided) to the MCO pin and test it.

 

[alessandro.breuza]

​@Pavel A.’s suggestion put me on the right path: routing HSE on MCO showed a lot of noise on external clock signals.

I will talk to PCB engineer, but I suspect a crosstalk from OCTOSPI lines which are routed near quartz.

 

Thanks for all hints,

Alessandro