HSE clock hardware design clarification
Hello everyone,
I am designing a board using STM32L496RE and I'm currently in the HSE clock design phase.
I have chosen a 16MHz crystal with CL 18pF. I have been following the AN2867 (https://www.st.com/content/ccc/resource/technical/document/application_note/c6/eb/5e/11/e3/69/43/eb/CD00221665.pdf/files/CD00221665.pdf/jcr:content/translations/en.CD00221665.pdf) and the formula at the end of page 12, setting CL=18pF, CL1=CL2. According to the datasheet of STM32L4x (https://www.st.com/resource/en/datasheet/stm32l496re.pdf), bottom of page 163, I can assume that CS=10pF.
Having done the calculations, I end up with CL1=CL2=16pF. However, I have looked at two other designs (not published by ST) where they have used the load capacitance in both branches of the oscillator, which makes me wonder if I should just set CL1=CL2=18pF.
Thank you, any clarification is appreciated,
Chris