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DSchm.3
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November 2, 2023
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HRTIM 100% duty cycle

  • November 2, 2023
  • 1 reply
  • 1688 views

Hello,
is there a solution to generate duty cycles between 0...100% with the HRTIM? I tried up-counting mode and center-aligned mode, but I wasn't able to achieve it. 

Regards
Dominik Schmid

This topic has been closed for replies.
Best answer by Peter BENSCH

HRTIM has a few limitations, e.g. it cannot generate PWM at real 0% or 100%, as can also be found in RM0440:

  • The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. The value 0x0000 can be written in CMP1 and CMP3 registers only, to skip a PWM pulse. See Section: Null duty cycle exception case for details
  • The maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock.

The second point concerns the requested 100%, which is always at least one HRTIM period smaller. And section Null duty cycle exception case says:

The high-resolution behavior is not supported for pulses narrower than 3 tHRTIM periods [...] and any value strictly below 3 periods of the fHRTIM clock [...] in the HRTIM_TIMxCMPy register is forbidden[...]. However, it is possible to skip an output pulse and have a null duty cycle by simply writing a null value in the following two registers: HRTIM_TIMxCMP1 and HRTIM_TIMxCMP3, if and only if the following conditions are met: [...]

For any other use case, this can be done by programming the SET and RESET events with the very same compare values, above 3 periods of the fHRTIM clock.

Does it answer your question?

Regards
/Peter

1 reply

Peter BENSCH
Peter BENSCHBest answer
ST Technical Moderator
November 2, 2023

HRTIM has a few limitations, e.g. it cannot generate PWM at real 0% or 100%, as can also be found in RM0440:

  • The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. The value 0x0000 can be written in CMP1 and CMP3 registers only, to skip a PWM pulse. See Section: Null duty cycle exception case for details
  • The maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock.

The second point concerns the requested 100%, which is always at least one HRTIM period smaller. And section Null duty cycle exception case says:

The high-resolution behavior is not supported for pulses narrower than 3 tHRTIM periods [...] and any value strictly below 3 periods of the fHRTIM clock [...] in the HRTIM_TIMxCMPy register is forbidden[...]. However, it is possible to skip an output pulse and have a null duty cycle by simply writing a null value in the following two registers: HRTIM_TIMxCMP1 and HRTIM_TIMxCMP3, if and only if the following conditions are met: [...]

For any other use case, this can be done by programming the SET and RESET events with the very same compare values, above 3 periods of the fHRTIM clock.

Does it answer your question?

Regards
/Peter

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