How to set up the adc sampling time.

[GHARI.1]

Hi,

I am using ADC of STM32H743ZI which is configured as 16 bit, ADC clock =36.5MHz,Tsampling=1.5cycles in continuous conversion mode . I am using DMA technique to collect the data using a buffer size of 4096 in circular mode.

The input is sine wave of peak to peak voltage =3.3V whose frequency varies from 1Hz to 20K Hz.

In debug mode when I observed data stored in buffer I am able reconstruct the signal back but accuracy is very less (sample to sample there is lot of voltage difference) for high frequencies.

Since Tsampling is 1.5cycles and Tconversion is 8.5Cycles and ADC clock is 36.5 MHz sampling speed would be 3.65Msamples/sec.

What might be the issue for this low accuracy whether DMA is not able to store this high sampling speed data or Tsamping is creating a problem. Can any one help me out solving this problem.

[KnarfB]

Use a timer with the desired sampling freq. like 48 kHz or more. Configure it such that its output trigger (TRGO) is its Update Event.

Use ADC Regular Conversion Mode and configure the Timer Output Event as External Trigger Conversion Source. Leave the DMA output as is.

Now, the ADC should be triggered precisely with the desired freq. and you should receive a clean signal in the buffer.

Consult the ref.man. for what timers and ADCs can be combined.

Haven't done it on H7 so there might be more to consider.

hth

KnarfB

[GHARI.1]

Instead of DMA can I use a buffer of that size and store the values into buffer when ever conversion complete trigger is raised?

[QSHAO.1]

The sampling time may be a reason of low accuracy of ADC.

based on the STM32H743ZI datasheet, the Rin (ADC input impedance) =max 50Kohm and Cadc (internal sampling and hold capacitor) = 4pF. so the RC time constant could be 200nS, and to reach 16bit resolution the sampling time could be about 11 time constant 2200ns >> current sampling time 1.5x(1/36.5MHz)= 42nS. so the sampling capacitor seem not be charged enough to reach 16bit resolution. ​

[QSHAO.1]

sorry I made a mistake that Rin is 170ohm instead of 50Kohm...

in this case the RC time is 0.17x4=0.68ns and 11 time constant is 7.8ns. the sampling time of 42ns is enough.

[GHARI.1]

Why we have to consider 11 time constants.

[QSHAO.1]

to reach 16bits resolution, the output of RC filter (sampling circuit) should be charged and reach "1- 1/(2^16)" of input.

at same time, the RC filter output is Vin x( 1- exp (- time of RC constant)), by calculation 11 time is needed to reach 16bit resolution. ​

[TDK]

> In debug mode when I observed data stored in buffer I am able reconstruct the signal back but accuracy is very less (sample to sample there is lot of voltage difference) for high frequencies.

If you're getting data back that looks like the expected signal, but with noise, there is no problem with DMA or the code.

Noise can come from many sources. At 3+ Msps, you're going to have to deal with some of it.

How much noise are you seeing? Can you show a plot of the original and the reconstructed signal?

Is this a custom board? Is the VREF+ line stable and does it have sufficient capacitance?

[GHARI.1]

I am using Nucleo-H743ZI2 standard board. I have plotted the data using usart communication with 250K baud rate which is very less compared to sampling speed so this is not accurate.

I am able to say that reconstruction is happening by observing the data in buffer by seeing its variation in debug mode.