How to remap CAN-Pins for a STM32F042 TSSOP20 Chip

[DRied]

Hi,

I'm going to use a STM32F042F6P in TSSOP20 - case for a application using CAN - connectivity. The low-pin-version of the STM32F042 demand to remap the CAN-pins to alternate pins.

I already discovered the hint for bit 4 (PA11_PA12_RMP) of SYSCFG_CFGR1 for repmapping PA11/PA12 to PA9/PA10 (pin 17/18 of the TSSOP20 chip), but unfortunately it simply doesn't work.

I checked my firmware with a LQFP32 type of the chip (NUCLEO-Board) with CAN - pins on PA11/PA12 - so everything seams to work properly. My idea was simply to change SYSCFG_CFGR1.4 - bit for the smaller case chip and have fun with the stuff.

Please can anybody tell me weather there is anything else to do transfer my CAN-Program from STM32F042K4U (LQFP32) to STM32F042F6P (TSSOP20), or is the remap-bit the only neccessary changing?

My second question is, does pin-remapping work with GPIOs to? As a test, I tried to remap PA11/PA12 to PA9/PA10 and to toggle PA11/PA12 then, but this didn't run too.

Thanks a lot for your help.

[Tesla DeLorean]

Don't you need to do the PA11/PA12 vs PA9/PA10 switch, and then set the AF4 for PA11/PA12 pin configuration?

https://www.st.com/resource/en/datasheet/stm32f042f6.pdf

[Tesla DeLorean]

 /* Enable GPIO TX/RX clock */
 __HAL_RCC_SYSCFG_CLK_ENABLE();
 __HAL_RCC_GPIOA_CLK_ENABLE();
 
 __HAL_REMAP_PIN_ENABLE(HAL_REMAP_PA11_PA12); // SYSCFG_CFGR1_PA11_PA12_RMP
 
 /* Enable CAN clock */
 __HAL_RCC_CAN1_CLK_ENABLE();
 
 /*##-2- Configure peripheral GPIO ##########################################*/
 /* UART TX GPIO pin configuration */
 GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 GPIO_InitStruct.Pull = GPIO_NOPULL;
 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 GPIO_InitStruct.Alternate = GPIO_AF4_CAN;
 
 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
...
 [e-mail]

[DRied]

Hello Clive,

thank you very much for your prompt reply.

I use the MIKROE C compiler, and they offer a routine for CAN - Setup including bit timing, pin setup etc. There AF4 configuration is done. With the LQFP - type it worked well.

But do you know whether one step is to be done before the other, or is that not important?

[Kraal]

Hi there,

Did you notice that Clive's example first enabled the clock for the SYSCFG ? Are you also enabling the clock for SYSCFG before changing bit 4 in SYSCFG_CFGR1 ?

[DRied]

Good morning Clive and Kraal,

thank you very much for your help again.

With your advice I was able to fix the problem.

I myself would never have come up with the idea of searching this corner for the cause of the error.

You were therefore a great help - thank you again.