How to optimize ADC accuracy

[hans5]

Posted on November 29, 2007 at 04:41

How to optimize ADC accuracy

[hans5]

Posted on May 17, 2011 at 12:18

Hi,

In the new datasheet (rev 4) a note is added below the ADC accuracy specifications (Table 46) stating:

''2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.''

Is it possible to give some indications of what performance increase could be achieved at what restrictions?

Regards,

Hans Rosenbrand

[hans5]

Posted on May 17, 2011 at 12:18

I think it is obvious that you get a better performance under restricted conditions.

I was hoping that, when ST adds a remark to the datasheet, they have some data justifying this remark.

So I assume they know what is the optimal VDD, frequency and VREF to operate the ADC with, and I hope they will share this information, so I can optimize my design. If they could also give some indication of the error reduction that could be achieved using these conditions, I would be very pleased...

Regards,

Hans Rosenbrand

[obtronix]

Posted on May 17, 2011 at 12:18

I don't know if ST will give you an answer to this, there are too many variables. But we have, in the past, characteristed A/D's and achieved 16 bit accuracy from a 10 bit A/D under VERY restricted conditions. It's hard to make an A/D that works over a wide range of conditions, but when you restict the conditions it gets very very good very fast.

There is some risk though, if ST decides to change the process they use the construct the chip a new batch of chips may all of sudden not meet your specification.