How to enable 100k cycles, instead of 10k cycles. [Resolved]

[SSaunders]

From RM0456-stm32u575585....

Flash section 7.3.8:

"... up to

256 Kbytes (32 pages) per bank feature an increased endurance of 100 kcycles, that can be used for data storage that usually needs more intensive cycling capability than code

storage. Any Flash page can be chosen to be cycled more than 10 000 times (up to 100 000 times). It is the application responsibility to limit the size of the Flash area cycled more than 10 000 times to 256 Kbytes per bank."

Perfect, 100k cycles is good for our use-case...

But I've been unable to find any registers, or any other documentation/notes/etc, that explain how to enable this, or how to select it, or really anything explaining it at all.

So.. How does this work?

And how do I enable this?

[Tesla DeLorean]

Yeah, the description isn't very helpful

Kind of implies that there's some spare memory it can remap, or that out of the bank with 1MB you could build something that could support 256KB (1/4), but you might need some block management, and reallocation scheme.

@STOne-32​ 

[Tesla DeLorean]

https://www.st.com/resource/en/application_note/an4894-eeprom-emulation-techniques-and-software-for-stm32-microcontrollers-stmicroelectronics.pdf

[SSaunders]

I mean, it seems they say the same thing in there again and again not explaining how to enable it..

And otherwise... yes. a Wear-leveling algorithm would otherwise work, but It'd also work better, if it was configured to also use the 100k-cycle thing... which is still unanswered.

(And yes, a ware-leveling algorithm does work too, but I don't really have the time to do that, nor integrate someone else's attempt of doing so)

[waclawek.jan]

My reading of the quote above is, that you don't need to perform wear leveling up to 100k cycles, as long as you stick to a handful of pages (namely 32).

The underlying reason may be, that while each individual FLASH cell can withstand 100k cycles with some reasonable resulting retention, the common HV source cannot withstand 100k cycles multiplied by number of all pages. Or anything else: I am not an ST insider.

Review also cycle-dependent parameters in DS.

JW

[Imen.D]

Hello,

I raised this post internally to the appropriate team for improving the docs.

Note that each Flash memory cell can be programmed and erased up to 100 000 times.

On STM32U5, can any Flash page be cycled more than 10 000 times?

Imen

[SSaunders]

Thank you for the rational of how it fails! It now makes sense and even gives further ideas of how to potentially increase reliability.

[StéphaneM]

Thanks Imen,

Note also that the description will be improved a bit in the next version of RM0456 (see below).

And in practice, nothing to do on user side from a firmware standpoint. Any Flash page can be cycled up to 100 000 times provided that this is limited to 32 pages per bank.

Stéphane

7.3.8 Flash memory endurance

Each flash memory page can be written and erased 10 000 or 100 000 times. A maximum of

32 pages (256 Kbytes) per bank feature this increased endurance of 100 kcycles. This

enhanced endurance can be used for data storage that usually needs more intensive

cycling capability than code storage.

Any flash page can be chosen to be cycled up to 100 kcycles. As soon as a page is above

10 kcycles, it is considered as high cycling page (even if not yet at 100 kcycles). The

application must take care not to exceed 32 pages cycled more than 10 000 times.

[Pavel A.]

> As soon as a page is above 10 kcycles, it is considered as high cycling page 

Hi @St�phaneM​ but how the "high cycling" is actually achieved? Does the MCU have 32 reserved flash pages or ECC storage and corrects errors transparently?

[waclawek.jan]

https://community.st.com/s/article/on-stm32u5-can-any-flash-page-be-cycled-more-than-10-000-times