How to detect interrupt by a timer?

[JAlca]

Hi all,

I know how to program a time base interrupt by a timer in HAL, but now I'm learning about do it in CMSIS, with a STM32F303CCT6 MCU.

My question is, in RM0316 doc, page 287, it talks about the Interrupts and Exceptions Vectors, wioth a total of 84 positions. Lets imagine I need to generate a time base interrupt qith the timer 7, who has a 55 position number.

What register I must set in order to let that interrupt happens, and what register I must look for in order to catch that interrupt?

(EXTI_IMR and EXTI_EMR are about 35 positions only)

I saw some tutorials about how to set external interrupts, but I didnt find any about this. Can someone point me to a tutorial or a doc?

[waclawek.jan]

Look into the device header in [CubeF3]\Drivers\CMSIS\Device\ST\STM32F3xx\Include\, you already have a symbol defined there such as

 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */

which you use to enable the interrupt and set its priority using the following CMSIS convenience functions:

 NVIC_SetPriority(TIM7_IRQn, 3);
 NVIC_EnableIRQ(TIM7_IRQn);

Then in the startup code you'll find a table pointing to the interrupt service routines, named similarly:

 .word TIM7_IRQHandler

so you write a function with the SAME name

void TIM7_IRQHandler(void) {
 // read out TIM_SR, clear it as soon as possible, and handle whatever interrupts have been indicated of the enabled ones
}

and that's your interrupt service routine (ISR) for this interrupt.

EXTI is just one of the interrupt sources - look at the table of exception vectors you've mentioned, you'll find how outputs from EXTI go into NVIC (some of them alone, some of them grouped).

I know of no good concise tutorial in this, most of the information is scattered in the basic documentation - the Programming Manual for Cortex-M4, which mostly copies portions of the ARM's Cortex-M4 Technical Reference Manual, and the same is then extended with some narrative in Joseph Yiu's books.

JW

[JAlca]

Thank you very much!,

I'm going to test. :)

[JAlca]

It works perfect! :)

[berendi]

The NVIC interrupt controller is part of the ARM Core, not an ST add-on, so it's documented in the Programming manual.

In order to enable and handle an interrupt, you'd need to set at least

• one or more interrupt enable bit in TIMx->DIER
• the corresponding bit in NVIC->ISER[]
• an entry in the vector table pointing to the handler function

Other registers relevant to interrupt handling are

• All of the NVIC registers of course
• PRIGROUP field in SCB->AIRCR
• SCB->VTOR
• BASEPRI and PRIMASK. These are not addressable, but special registers accessed with the MSR and MRS instructions.