How to ahcieve Reset Mode + Gated Mode on Timer with STM32F3

[Zheng Liang]

I need to generate an interrupt if a low level is hold more than specifical time.

I wanna achieve that executing Timer reset and start counting on failing edge, stop on rasing edge, if the duration is larger a compare register, a interrupt generated and then handle it.

Could I achieve that by only configuring the Timer and without CPU or DMA cycle?

[TDK]

I think so.

• Set up a timer in gated mode with the signal as input.
• Also connect the input to the timer ETR pin and have it reset the timer on falling edge.
• Set up the CC1 channel with a value which corresponds to the threshold for a pulse being too long. Configure this to trigger an interrupt.

Note that it'll trigger as soon as the pulse reaches the threshold, as opposed to when the pulse terminates.

[waclawek.jan]

@TDK​ ,

> Set up a timer in gated mode with the signal as input.

> Also connect the input to the timer ETR pin and have it reset the timer on falling edge.

Don't these two things require SMCR.SMS to be in two different settings?

JW

[TDK]

> Don't these two things require SMCR.SMS to be in two different settings?

Yes. Darn. And my guess is the OP already knows this by the question title asking for "Reset Mode + Gated Mode". So they, and you, are one step ahead.

I still feel like it may be possible, but I can't immediately see how to do it.

[Zheng Liang]

Yes, it's possible with DMA or CPU on only one timer, needs to change the SMS when one edge detected, but with extra cost and potential risk.

​

@Community member​ 's two timers mode is beautiful, this could achieve only in timer without CPU/DMA cycle, you can check this out.

[waclawek.jan]

> I still feel like it may be possible,

I don't think so. The timer hardware has fixed and limited functionality, more complex issues are to be handled in software. I usually try to pull out tricks using DMA, but it's "forbidden" here, and the combined slave-mode modes like they are in the newer timers, are not available in TIM3.

I can imagine using one timer as the gated clock source, routing its output externally to ETR input of other timer in external clock mode 2, where the slave-mode controller is used for reset (i.e. input signal goes both to first and second timers' CHx pin, to be input to the slave-mode controller - this signal maybe can be routed internally). We spent 4 pins and it still "suffers" from what you've identified above:

> it'll trigger as soon as the pulse reaches the threshold, as opposed to when the pulse terminates.

and I don't quite see how that one can be fulfilled.

JW

[Zheng Liang]

Yes, with one timer, I think it's hard to achieve that.

Your two timers model is clever, the smartest point is "external clock mode 2" on slave timer, that means add another controllable input and has no collision with SMS. This approach cost 4 pins but with time-cost saved exchange, it's brilliant.

Thanks for your help, I will try it soon.