How to achieve maximum system clock (168MHz) in stm32f446zet

[ANNU CHERIAN]

Posted on August 18, 2017 at 06:47

RCC->APB1ENR |= (1<<28);

PWR->CR |= (PWR_CR_VOS);

               

RCC->CR |= (1<<0);

RCC->CR |= (RCC_CR_HSICAL_4);                                   //

Internal high-speed clock calibration

RCC->CFGR |= RCC_CFGR_SW_HSI;                              //

HSI oscillator selected as system clock

RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;                      //

APB high-speed prescaler (APB2)

RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;                      //

APB Low speed prescaler (APB1)

RCC->CFGR |= RCC_CFGR_HPRE_DIV1;                        //

AHB prescaler

RCC->CR &= ~(1<<24);                                                       // 

PLL OFF

RCC->PLLCFGR &= ~(1<<22);                                           //

HSI clock selected as PLL

RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLM;        

RCC->PLLCFGR |= RCC_PLLCFGR_PLLM_4;                  //

Division factor for the main PLL (PLL) input clock (16)

RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLN;             

RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_4;                  //

Main PLL (PLL) multiplication factor for VCO (336)

RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_6;

RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_8;          

RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLP;                

RCC->PLLCFGR |= RCC_PLLCFGR_PLLP_1;                 // Main PLL (PLL) division factor for main system clock(2)

RCC->CR |= (1<<24);                                                         // enable PLL       

while(!(RCC->CR & RCC_CR_PLLRDY));                       // waiting for PLL lock

RCC->CFGR |= RCC_CFGR_SW_PLL;                           // PLL_P selected as system clock

Above code shows configuration to achieve maximum system clock (168MHz) , but during running time on keil uvision5 compiler  shows 'cannot access memory' . Please suggest a method to solve this issue .......

#stm32f446-system-clock

[Jan Waclawek]

Posted on August 18, 2017 at 12:56

Are you sure Keil's complaint is related to these lines? Are you trying to access external memory with the debugger? (I don't use Keil so these are blind shots)

JW

[Tesla DeLorean]

Posted on August 18, 2017 at 16:01

Yikes! That's hideously inefficient code, thought the point of this level of programming was to be minimal/optimal.

You'll need wait states for the FLASH

You'll want to avoid errata/hazards of enabling clocks and immediately touching the same peripheral.

Bunch of assumptions about initial conditions.

[ANNU CHERIAN]

Posted on August 19, 2017 at 09:05

This code work for system clock upto 142MHz by changing the value of PLL_N . On increasing further, error 'Cannot access memory' arises.

I am using STM32F446 Nucleo 144 Board.

[Tesla DeLorean]

Posted on August 19, 2017 at 14:27

{

  uint32_t pll_n = 360, pll_p = 2, pll_m = 16, pll_q = 7, pll_r = 7;

  RCC->APB1ENR |= RCC_APB1ENR_PWREN;

  RCC->CFGR |=  RCC_CFGR_HPRE_DIV1  | /* HCLK = SYSCLK / 1*/

                RCC_CFGR_PPRE2_DIV2 | /* PCLK2 = HCLK / 2*/

                RCC_CFGR_PPRE1_DIV4;  /* PCLK1 = HCLK / 4*/

  /* Select regulator voltage output Scale 1 mode, System frequency up to 168..180 MHz */

  PWR->CR |= PWR_CR_VOS;

  /* Configure the main PLL */

  RCC->PLLCFGR = pll_m | (pll_n << 6) | (((pll_p >> 1) - 1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSI) | (pll_q << 24) | (pll_r << 28);

  RCC->CR |= RCC_CR_PLLON; /* Enable the main PLL */

  while((RCC->CR & RCC_CR_PLLRDY) == 0); /* Wait till the main PLL is ready */

  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */

  PWR->CR |= PWR_CR_ODEN;

  while((PWR->CSR & PWR_CSR_ODRDY) == 0);

  PWR->CR |= PWR_CR_ODSWEN;

  while((PWR->CSR & PWR_CSR_ODSWRDY) == 0);

  /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

  FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN |

    FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY_6WS; // 5WS Might work

  /* Select the main PLL as system clock source */

  RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

  RCC->CFGR |= RCC_CFGR_SW_PLL;

  /* Wait till the main PLL is used as system clock source */

  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

}

[ANNU CHERIAN]

Posted on August 24, 2017 at 08:47

Thank You Clive .Maximum clock frequency (180MHz) achieved when enabling over drive and FLASH .