How many STM32 timers/channels are required to generate 8 synchronized PWM outputs with 4 PWM feedback inputs?

[Darvin]

Hi STM32 Community,

I am currently selecting an STM32 MCU for a timing-control application and would like some guidance on the required timer architecture.

My requirement is:

• Input trigger: 45 Hz, 50% duty-cycle signal.
• After receiving the trigger, the STM32 should generate 8 PWM outputs with a configurable delay.
• The required trigger-to-output delay is approximately 0–3 µs.
• PWM1–PWM4: 45 Hz, 25% duty cycle
• PWM5–PWM8: 45 Hz, 25% duty cycle
• The 8 outputs need to be synchronized according to the timing sequence shown in the attached diagram.
• In addition, I receive 4 feedback PWM inputs:
  • Feedback 1–4: 45 Hz, 25% duty cycle
  • These feedback signals need to be measured/captured by the STM32.

My main question is:

What is the recommended STM32 timer architecture for this requirement?

Specifically:

1. How many timer peripherals would I need?
2. Can I use two timers with 4 PWM channels each to generate the 8 PWM outputs?
3. Can a third timer with 4 input-capture channels be used to measure the 4 feedback PWM signals?
4. What is the recommended method to achieve the 0–3 µs trigger-to-output delay using hardware timers rather than software delays?
5. Are there any STM32 timer limitations or channel/pin-mapping issues I should consider when selecting the MCU?

   I would appreciate any recommendations regarding the suitable STM32 timer architecture or specific STM32 devices that would be appropriate for this application.

   I have attached the timing diagram for reference.

[TDK]

The output signals you list are identical to each other for each of the 4 sets of channels. They don’t need to be separate channels.

But you’ll need 3 timers.

Use combined PWM mode to set the 0-3us delay. Note that a 0 us delay is impossible--it takes a few ticks for signals to propagate.