How many AHB cycle required to perform memory to memory DMA after EN bit enabled?

[Test User]

Posted on July 08, 2018 at 12:10

How many AHB cycle required to perform memory to memory DMA after EN bit enabled?

I'm checking the STM32F4xx_DSP_StdPeriph_Lib_V1.8.0\Project\STM32F4xx_StdPeriph_Examples\DMA\DMA_FLASHToRAM example and after the DMA is enabled there are some code which inits the NVIC controller. So I think at least 20-50 cycle needed before starting the mem to mem copy (or the copy has itself delay)

  /* DMA Stream enable */

  DMA_Cmd(DMA_STREAM, ENABLE);

  /* Check if the DMA Stream has been effectively enabled.

     The DMA Stream Enable bit is cleared immediately by hardware if there is an

     error in the configuration parameters and the transfer is no started (ie. when

     wrong FIFO threshold is configured ...) */

  Timeout = TIMEOUT_MAX;

  while ((DMA_GetCmdStatus(DMA_STREAM) != ENABLE) && (Timeout-- > 0))

  {

  }

   

  /* Check if a timeout condition occurred */

  if (Timeout == 0)

  {

    /* Manage the error: to simplify the code enter an infinite loop */

    while (1)

    {

    }

  }

  /* Enable the DMA Stream IRQ Channel */

  NVIC_InitStructure.NVIC_IRQChannel = DMA_STREAM_IRQ;

  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;

  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;

  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

  NVIC_Init(&NVIC_InitStructure);     

}

[waclawek.jan]

Posted on July 08, 2018 at 14:13

How many AHB cycle required to perform memory to memory DMA after EN bit enabled?

I don't think this is different from 'normal' DMA, except that the trigger is present all the time until the whole transfer is finished. See AN4031. I did not time this but I guess the minimum will be around 8 cycles per transfer.

JW

[Test User]

Posted on July 09, 2018 at 07:47

After enabling the DMA how many C lines can I write in the program? See my previous code.

[waclawek.jan]

Posted on July 09, 2018 at 09:15

I would enable the transfer completion interrupt before enabling the DMA.

JW

[Test User]

Posted on July 09, 2018 at 10:11

Yes, but this is an official example from STM.

[waclawek.jan]

Posted on July 09, 2018 at 14:07

One more thing: it's enough to enable the TC interrupt in the stream's control register. When the transfer is finished, the TC flag gets set in the DMA status register, and even if the respective interrupt is not enabled in NVIC at that moment, as soon as it is enabled anytime later, it will trigger the interrupt.

So I take back what I've said above: this example is OK (even if I would do things differently).

JW