How do you trigger dual-core halting on an STM32H755BI?

[DFay.2]

I'm trying to get my SWD debugger to halt both cores when debugging one of them, but by default it appears to only halt a single core. Looking into the reference manuals for the H755 I see section "63.5.3 Cross Trigger Interfaces (CTI) and matrix (CTM)" which seems to cover this capability, but I am unable to find the base address of the CTI registers. Does anyone know where to find the base address for these registers or know of a way of getting both cores to halt when using a debugger?

[FBL]

Hello @Community member​,

According to the reference manual, the system-level CTI and the Cortex M4 CTI are accessible to the debugger via the system access port and associated APB-D

1. In section 63.4.2 Access ports, you can find that debug access port access for each core to be configured in your software.
2. You can refer to AN5286 and AN5361, both available on st.com which explain how to proceed to debug dual core with IAR™ EWARM (AN5286), MDK-Arm (AN5286) and STM32CubeIDE (AN5361)

For more details you can check STM32 microcontroller debug toolbox - Application note

Hope this helps!