Hi @CDesh & @KnarfB ,
Comparing both reference manuals of both STM32L4 and STM32L0 and precisely RCC_CSR register, I noted that bit 27 is described as following:
- STM32L4
- Bit 27 BORRSTF: BOR flag. Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit.
- 0: No BOR occurred
- 1: BOR occurred
- STM32L0
- Bit 27 PORRSTF: POR/PDR reset flag. This bit is set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.
- 0: No POR/PDR reset occurred
- 1: POR/PDR reset occurred
So either for L4 or L0, the flag is the same and it is set when a power reset occurs.
In STM32L0, BOR is not available on all devices.
So for both STM32L0 & STM32L4, we can identify POR/PDR/BOR condition based on the bit 27 of RCC_CSR register.
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-Amel
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