How can represent logical gates in software of STM32F429I?

[AAbed.1]

Hi All;

I am working on an STM32F429I timer (PWM-mode1) to obtain two signals then I want to use AND gate inside the program (the input is the two signals come from timer Ch1 &Ch2) and designate one pin to be the final output.

[Tesla DeLorean]

HAL_GPIO_WritePin(OUT_PORT, OUT_PIN, ( HAL_GPIO_ReadPin(IN_PORT1, IN_PIN1) && HAL_GPIO_ReadPin(IN_PORT2, IN_PIN2)) ? GPIO_PIN_SET : GPIO_PIN_RESET);

[AAbed.1]

is that ok

HAL_GPIO_WritePin(GPIOG,GPIO_PIN_9, ( HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_5) && HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_8))? GPIO_PIN_SET : GPIO_PIN_RESET);

[AAbed.1]

Where can I put that

inside while(1) (infinite loop)?

[Tesla DeLorean]

There, or some other periodically called function, your call.

Most would just solder a part on the board, or use diodes, to achieve functionality at wire speeds.

[TDK]

I don't believe there is a way to do this in hardware. You can do it in software as clive1 says, but there is going to be a delay between when the signal changes and when your output pin changes.

If a delay is okay and your CPU is busy doing other things, one option is to set the two pins as interrupts and within the interrupt, read the value of the two pins and update the output. The delay for this would be around 30 ticks if done efficiently.

[turboscrew]

74C08 has propagation delay 15-20 ns, so using SW is not so bad - relatively speaking...

Edge triggered interrupts (both edges) for both inputs and the interrupt routine (assembly) just reads the inputs and writes the output.

Takes somewhat longer than a logic chip, but not that dramatically.

 We're still talking about tens of nanoseconds.

[waclawek.jan]

Newer STM32 models implementation this particular function in the timer, see e.g. 'L4, Combined and Asymmetric modes in timers.

In the 'F4, you could do tricks with DMA or maybe master-slave connection of timers, or simply a different time run with the same period but phase shifted, to achieve a waveform similar to what you desire, whether some of this is suitable depend on the details of the application.

JW

[berendi]

When two channels of a timer are in PWM mode 1, then the software equivalent of an AND gate is finding the minimum of the two duty cycle values.

The hardware solution is to configure both pins as open drain outputs with pullups, internal or external, and wire them together.

[AAbed.1]

Thanks for your replays , but Here in this picture, you can find what I want .

So, is that possible to represent NOT and AND gates by Software instead of HW.

Thanks

I will hear from you

[henry.dick]

yes.

[AAbed.1]

Do you have example about that

Thanks

[S.Ma]

Why trying to do an "AND"? just generate 2 waveforms using DMA on channel toggle in circular pattern with table length adjust...

There is no smartio, so integrate the burst of pulses in the generation to each channel.

[AAbed.1]

I want to design the following signal ---->>>>

[S.Ma]

If you use the same timer for the compare toggles, you will be guaranteed synchronized generation.

[TDK]

Assuming your waveform is periodic, it's equivalent to starting the first pulse at t=0 and the second pulse at T=T/2. I'm sure you could manage that with two synchronized timers. Not sure about two channel within the same timer.

You could even keep the centers at 0.25T and 0.75T using center-aligned mode.