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wuhaibin011
wuhaibin011
Associate II
February 7, 2011
Question

how can i deal with 105's clock?

  • February 7, 2011
  • 3 replies
  • 800 views
Posted on February 07, 2011 at 08:01

how can i deal with 105's clock?

    This topic has been closed for replies.

    3 replies

    js23
    js23
    Associate III
    May 17, 2011
    Posted on May 17, 2011 at 14:24

    When USB is used, PLLCLK must be 48MHz or 72Mhz. PLLCLK is the source for SYSCLK and this is again the source for APB2.

    This means: APB2 can only be 48MHz or 72MHz, too (or fractionals of these frequencies). 64MHz will not be possible.

    js23
    js23
    Associate III
    May 17, 2011
    Posted on May 17, 2011 at 14:24

    Yep. When SYSCLK is 72MHz, fastest ADC speed is 12MHz. This means max. 857 kSamples/s (= 1.17µs conversion time).

    wuhaibin011
    wuhaibin011Author
    Associate II
    May 17, 2011
    Posted on May 17, 2011 at 14:24

    Thank you for your answer.

    i have to find to another way to finish the project.

    and from your answer ,i can also get a message:  when i use the USB ,the ADC

    can't be setted to 56M,  so the ADC  will not get the fasted speed.

    is it right?

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