HEEEEEELP With FSMC SRAM interface

[zeros_and_ones1991]

Posted on February 19, 2014 at 04:39

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[troy1818]

Posted on February 19, 2014 at 10:58

Hi t.muhammad,

I guess you cannot trust the examples that you find online:

http://www.coocox.org/show_exam/FSMC/455.html

According to me (assuming that stm32f4 is used), fsmc bank1 is not operating with NE2 as chip select (PG9

). It is using NE1 (PD7).

I would recommend making sure that the chip select is going low when the actual write is made to the SRAM.

Also, usually you would like to make the fsmc address volatile, so that the compiler is not optimizing it out.

 *(volatile uint16_t *) (0x64000000)=0xAADD; // break point here

Hope this helps.

Regards,

/rygelxvi

[Tesla DeLorean]

Posted on February 19, 2014 at 13:50

Perhaps it's not a software/configuration issue. So when you've exhausted that approach maybe you could go over the connectivity you've achieved.

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[zeros_and_ones1991]

Posted on February 19, 2014 at 21:13

Thx for ur reply guys , .... well I tried to test the signals with uni scope today , n they seem to be working perfectly ...... for the while statement , the CS gave square wave which is great , and when i read , the NOE gave the same square wave , so now the interface is working as hardware , but the data is corrupted ...... when i write then read , its not the same data ......... any idea?

[troy1818]

Posted on February 20, 2014 at 09:38

Hi again,

If the data is not correct I would take a close look at the data and address together with NOE and NWE with oscilloscope. Make sure that these are correct and that the timings are correct compared to the ones in the datasheet for the memory. Also ALE and CLE if you have them. If everything is ok here, then I would look at the HW, especially for soldering problems. If you could test with another board would be nice of course.

Regards,

/rygelxvi

[zeros_and_ones1991]

Posted on February 20, 2014 at 22:10

FINALLY ............ I got it working guys ....... The Stupid wave share (from which i ordered that SRAM board) ........ had wrong schematic ...... On the board there 're CS1 , CS2 , CS3 , NE2 , NE3 ...... so As the schematic stated the CS of the SRAM is CS1 , but it turned out to be NE3 , may be they made that board to be interfaced directly to another development board , but they should have stated it really in the schematic ........ Now i can read and write at around 40 MHz , with the Core running at 120 MHz ........ pretty good.

Thx for ur help guys.