Hardware trigger

[linas2]

Posted on March 31, 2013 at 20:24

Hello, i have CLK which is generated by ADC, and i need to generate SI signal as shown in this picture. I used software version, but it is very unstable, and if i recompile that, it can completely mess up timing.

GPIOA_Pin15 connected to CLK

while(GPIOA->IDR < 
32765
); // wait if CLK is low, 

while(GPIOA->IDR > 32765); // wait if CLK is high, when i go out from this loop CLK should be low
Delay(6); // wait a bit, it is 6x ''nop''
GPIOA->BSRRL= GPIO_Pin_10; // Set Si high
Delay(6); // wait a bit
GPIOA->BSRRH= GPIO_Pin_10; //Set SI low

Can i do it by using STM32F4 hardware ? (now stm32f4 core is clocked to 255MHz)

[linas2]

Posted on April 02, 2013 at 16:54

ok, after long surfing i found why my code is slow.

as it turns out, FIFO Load clock is 8MHz, unload clock with some two floating MAC operation is 7.999MHz, that means that mcu is fast as it can be for this task. but biggest lag is float to integer conversion

while(1)
{
while(GPIOA->IDR < 
32766
);
GPIOD->BSRRL= GPIO_Pin_13; 
while(GPIOA->IDR > 32766);
while(GPIOA->IDR < 
32766
);
GPIOD->BSRRH= GPIO_Pin_13;
imag=0;
real=0;
i=0;
while(i<
128
)
{
while(GPIOC->IDR < 
32766
);
CLK_LOW;
CLK_HIGH;
k
=
GPIOB
->IDR;
real+=k*cosinusas[i];
imag-=k*sinusas[i];
i++;
}
faze=faze-(0.2*Phase(imag,real));

DAC_DATA=(int)(faze*375+32767);

} 

if i don't use

DAC_DATA=(int)(faze*375+32767);

loop speed is 58KHz, if i add DAC_DATA line, speed goes down to 40KHz, why ? How can i get it done faster ? DAC_DATA for integer is as fast as FSMC,it don't slow loop at all. any workaround for this problem ?