handling multiple interrupts on same EXTI line in STM32

[muhammaduzairafzal45]

Posted on December 12, 2012 at 09:13

I am doing a project using STM32F103. I have a scenario. I want to use PG1 and PF1 pins as falling edge interrupt pins which are on same EXTI1 line. Problem is that only one pin which is configured after first one using GPIO_EXTILineConfig() function, which is PF1 in my below code, is correctly going to ISR while PG1 is not going to ISR on interrupt at all. If I configure PG1 after PF1  using GPIO_EXTILineConfig() function

 then only PG1 goes to ISR. What is wrong? How to handle 2 or more interrupts on same EXTI line? Also please tell can I configure PG1 on rising edge interrupt and PF1 on falling edge at same time? My code is:

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;

GPIO_Init(GPIOG, &GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;

GPIO_Init(GPIOF, &GPIO_InitStructure);

GPIO_EXTILineConfig(GPIO_PortSourceGPIOG,GPIO_PinSource1);

GPIO_EXTILineConfig(GPIO_PortSourceGPIOF,GPIO_PinSource1);

// Configure EXTI1 line 

  EXTI_InitStructure.EXTI_Line = EXTI_Line1;

  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;

  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  

  EXTI_InitStructure.EXTI_LineCmd = ENABLE;

  EXTI_Init(&EXTI_InitStructure);

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);

  NVIC_InitStructure.NVIC_IRQChannel = EXTI1_IRQn;

  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x00;

  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x07;

  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

  NVIC_Init(&NVIC_InitStructure);

void EXTI1_IRQHandler(void)

{

if(EXTI_GetITStatus(EXTI_Line1) != RESET)

{

/*   my implementation of ISR */

EXTI_ClearITPendingBit(EXTI_Line1);

}

}

[Tesla DeLorean]

Posted on December 12, 2012 at 14:01

I'd be surprised if your scheme was viable. Why can't you use different/independent pins?

[muhammaduzairafzal45]

Posted on December 12, 2012 at 14:44

Actually I cannot afford to use an independent EXTI line because I am using a lot of interrupts in my project. I have to use multiple interrupts on same EXTI. This problem is a general scenario. What is the method to use multiple interrupts on same EXTI? Does this mean that I can use only one GPIO pin 0 (from PA.00,PB.00,PC.00,PD.00,PE.00 etc.) to connect to EXTI0 line? If so then does not it a strange thing that I can only configure one pin instead of multiple pins to same EXTI? Please tell me the method to solve this issue.

[Tesla DeLorean]

Posted on December 12, 2012 at 18:45

You should perhaps read the RM0008 Reference Manual, and specifically the page describing the AFIO_EXTICR1 register. I'm not going to get into a silicon implementation argument about about how it might or could have gotten implemented, and how flexible/inflexible you find it.

Historically, if you run out of internal resources you'd need to add external logic to latch, decode and prioritize the interrupt sources. ie have one pin generate an interrupt, and use other pins to read a source number in binary.

You have 16 external sources, assign your pins accordingly.

[hfs99]

Posted on December 13, 2012 at 03:33

Hardware details: AFIO->EXTICR1 bits[7..4] are called EXTI1. These 4 bits select which port is used for EXTI1. If you call GPIO_EXTILineConfig() multiple times, each call over-writes those bits with a new value.

I seem to recall that some of the NXP ARM7 chips like the LPC213x have (part of) the behavior you're looking for; the pins are essentially OR-ed or AND-ed to produce the interrupt. I don't know if any of their cortex offerings behave the same. (It sounds as if you're way beyond that stage of your project anyway.)

[tinymanta]

Posted on December 19, 2012 at 11:10

The EXTI lines dedicated to the GPIO pins can be mapped to any combination of port pins. This is done through four configuration registers. In these registers each EXTI line is mapped to a four bit field. This field allows each EXTI line to be mapped onto any of the IO ports, so for example EXTI line zero can be mapped onto pin 0 of port A, B, C, D.... This scheme allows any external pin to be mapped to an interrupt line.

[Tesla DeLorean]

Posted on December 19, 2012 at 13:52

The OP is looking to map multiple PINS to a singular EXTI line, which as stated earlier is impractical.

[muhammaduzairafzal45]

Posted on December 19, 2012 at 14:39

Thanks all of you for support. All this discussion concludes,like said by

clive1

and sutherland

, that same pins of multiple ports cannot be connected to same EXTI. We have to use external 'and or' logic to tackle this problem.