H743 PB4 defaults to a high level issue.

[奥特曼9527]

When Pb4 is reset, it is at a high level. Can't this be configured in the hardware? It's too disgusting. The PCB has been designed and encountered this pit.

[Andrew Neil]

PB4 is NRST - it's active low, so you'd expect its default state to be high.

This power-up state is clearly documented:

https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page=533

 

 

[奥特曼9527]

I know what you're saying, but it's frustrating to see that such high-end chips don't have internal settings. It's common for us to use MCU to control IO high and low levels, and this kind of setting makes users make mistakes. I think it's not just me, many users have used it before.

[Andrew Neil]

---

@奥特曼9527 wrote:

it's frustrating to see that such high-end chips don't have internal settings. 

---

Do you know of any chips which do have such settings?

It's a standard part of the design process to understand what the power-up state of the IOs will be, and design the rest of the circuit accordingly.

 

You should be able to find the (approximate) value of the internal pullup in the datasheet.

[TDK]

In addition to @Andrew Neil 's comments: no, it cannot be configured in hardware. An external pulldown could help here.

[奥特曼9527]

How many resistors are suitable for external pull-down? I don't know what is suitable for internal pull-up,

[Andrew Neil]

If you pull NRST low, that will keep the microcontroller in reset - it will never start!