H723ZG Nucleo ADC clock/noise question
After assembling the X3 external 25MHz crystal and 2 caps and generating initialize code for 550MHz clock with CubeMX my NUCLEO-H723ZG board runs fine, except ADC. It is very noisy. The CubeMX configured the clock for ADC = 96.000671 MHz (PLL2P). In the datasheet of the MCU the maximum ADC clock is 50MHz (BOOST=3) Is this okay or I found a bug in CubeMX?
I use ADC1 and ADC2 to sample two 150Hz 2Vpp sine wave signals. There is 100us phase difference between signals. (Blue is delayed) I start the ADCs simultaneously from TIMER1. When HAL_ADC_ConvCpltCallback() is called I read the ADC1 (yellow) and ADC2 (bule) conversion results. I generate the ADC1 – ADC2 signal with DAC1. Because the ADCs are in 16-bit mode but the DAC1 can handle 12-bit numbers only I right shift the ADC result by 4 and subtract the 12-bit numbers.
uint32_t difference = (chn1Data >> 4) - (chn2Data >> 4);I write the value of difference variable into the DAC1. This is the green channel.
- Yellow: A signal (1V)
- Blue: B signal (1V)
- Orange: Comparator output (1V) It compares A input signal to +1.25V.
- Green: A-B signal on output of 12-bit DAC1 (100mV)
I also tried the 64-bit oversampling but it did not help or I configured something faulty:
hadc1.Init.OversamplingMode = ENABLE;
hadc1.Init.Oversampling.Ratio = 1 << 6;
hadc1.Init.Oversampling.RightBitShift = ADC_RIGHTBITSHIFT_6;
hadc1.Init.Oversampling.TriggeredMode = ADC_TRIGGEREDMODE_SINGLE_TRIGGER;
hadc1.Init.Oversampling.OversamplingStopReset = ADC_REGOVERSAMPLING_RESUMED_MODE; With these settings I could get back the (integer) average of 64 ADC conversions of every sample point. Am I right?
Anybody has any idea why the difference signal so terrible?
Thanks,
Louis
